An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost (among other things); because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.
An ISA defines everything a machine language programmer needs to know in order to program a computer. What an ISA defines differs between ISAs; in general, ISAs define the supported data types, what state there is (such as the main memory and registers) and their semantics (such as the memory consistency and addressing modes), the instruction set (the set of machine instructions that comprises a computer's machine language), and the input/output model.
Computer architectures are often described as n-bit architectures. Today n is often 8, 16, 32, or 64, but other sizes have been used (including 6, 12, 18, 24, 30, 36, 39, 48, 60). This is actually a simplification as computer architecture often has a few more or less "natural" datasizes in the instruction set, but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are the 8080, Z80, MC68000 as well as many others. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as the IBM System/360 Model 30, have smaller internal data paths, while others, such as the 360/195, have larger internal data paths. The external databus width is not used to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses; the NS32764 had a 64-bit bus, and used 32-bit register. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.
The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture will allow
A := B + C
to be computed in one instruction.
A two-operand architecture will allow
A := A + B
to be computed in one instruction, so two instructions will need to be executed to simulate a single three-operand instruction.
A := B A := A + C
An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little-endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big-endian architectures instead arrange bytes with the most significant byte at the lowest-numbered address. The x86 architecture as well as several 8-bit architectures are little-endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big-endian (ARM was little-endian), but many (including ARM) are now configurable as either.
Endianness only applies to processors that allow individual addressing of units of data (such as bytes) that are smaller than the basic addressable machine word.
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Usually the number of registers is a power of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of register files of architectures, mostly to simplify indexing modes. This table only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program pointer (PC). Those are not counted unless mentioned. Note that some architectures, such as SPARC, have register windows; for those architectures, the count below indicates how many registers are available within a register window. Also, non-architected registers for register renaming are not counted.
Note, a common type of architecture, "load–store", is a synonym for " Register–Register" below, meaning no instructions access memory except special – load to register(s) – and store from register(s) – with the possible exceptions of atomic memory operations for locking.
The table below compares basic information about instruction sets to be implemented in the CPU architectures:
|Instruction encoding||Branch evaluation||Endian-
|6502||8||1975||1||Register–Memory||CISC||3||Variable (8- to 32-bit)||Condition register||Little|
|6809||8||1978||1||Register–Memory||CISC||9||Variable (8- to 32-bit)||Condition register||Big|
|680x0||32||1979||2||Register–Memory||CISC||8 data and 8 address||Variable||Condition register||Big|
|8080||8||1974||2||Register–Memory||CISC||8||Variable (8 to 24 bits)||Condition register||Little|
||Variable (8-bit to 128 bytes)||Compare and branch||Little|
|x86||16, 32, 64
||Variable (8086 ~ 80386: variable between 1 and 6 bytes /w MMU + intel SDK, 80486: 2 to 5 bytes with prefix, pentium and onward: 2 to 4 bytes with prefix, x64: 4 bytes prefix, third party x86 emulation: 1 to 15 bytes w/o prefix & MMU . SSE/MMX: 4 bytes /w prefix AVX: 8 Bytes /w prefix)||Condition code||Little||x87, IA-32, MMX, 3DNow!, SSE,
SSE2, PAE, x86-64, SSE3, SSSE3, SSE4,
BMI, AVX, AES, FMA, XOP, F16C
|Alpha||64||1992||3||Register–Register||RISC||32 (including "zero")||Fixed (32-bit)||Condition register||Bi||, , ,||No|
|ARC||16/32/64 (32→64)||ARCv3||1996||3||Register–Register||RISC||16 or 32 including SP
user can increase to 60
|Variable (16- or 32-bit)||Compare and branch||Bi||APEX User-defined instructions|
||Fixed (32-bit)||Condition code||Bi||NEON, Jazelle, ,
||Thumb: Fixed (16-bit), Thumb-2:
Variable (16- or 32-bit)
|Condition code||Bi||NEON, Jazelle, ,
|Arm64/A64||64||ARMv8-A||2011||3||Register–Register||RISC||32 (including the stack pointer/"zero" register)||Fixed (32-bit), Variable (32-bit or 64-bit for FMA4 with 32-bit prefix)||Condition code||Bi||SVE and SVE2||No|
16 on "reduced architecture"
|Variable (mostly 16-bit, four instructions are 32-bit)||Condition register,
on an I/O or
compare and skip
|AVR32||32||Rev 2||2006||2–3||RISC||15||Variable||Big||Java Virtual Machine|
8 data registers
8 pointer registers
4 index registers
4 buffer registers
|Variable (16- or 32-bit)||Condition code||Little|
|CDC Upper 3000 series||48||1963||3||Register–Memory||CISC||48-bit A reg., 48-bit Q reg., 6 15-bit B registers, miscellaneous||Variable (24- or 48-bit)||Multiple types of jump and skip||Big|
Central Processor (CP)
|60||1964||3||Register–Register||n/a[b]||24 (8 18-bit address reg.,
8 18-bit index reg.,
8 60-bit operand reg.)
|Variable (15-, 30-, or 60-bit)||Compare and branch||n/a[c]||Compare/Move Unit||No||No|
Peripheral Processor (PP)
|12||1964||1 or 2||Register–Memory||CISC||1 18-bit A register, locations 1–63 serve as index registers for some instructions||Variable (12- or 24-bit)||Test A register, test channel||n/a[d]||additional Peripheral Processing Units||No||No|
|32||2000||1||Register–Register||VLIW||Variable (64- or 128-bit in native mode, 15 bytes in x86 emulation)||Condition code||Little|
|64||Elbrus-4S||2014||1||Register–Register||VLIW||8–64||64||Condition code||Little||Just-in-time dynamic translation: x87, IA-32, MMX, SSE,
SSE2, x86-64, SSE3, AVX
|eSi-RISC||16/32||2009||3||Register–Register||RISC||8–72||Variable (16- or 32-bit)||Compare and branch
and condition register
|64||2001||Register–Register||EPIC||128||Fixed (128-bit bundles with 5-bit template tag and 3 instructions, each 41-bit long)||Condition register||Bi
|Intel Virtualization Technology||No||No|
|M32R||32||1997||3||Register–Register||RISC||16||Variable (16- or 32-bit)||Condition register||Bi|
|Mico32||32||?||2006||3||Register–Register||RISC||32||Fixed (32-bit)||Compare and branch||Big||User-defined instructions||Yes||Yes|
|MIPS||64 (32→64)||6||1981||1–3||Register–Register||RISC||4–32 (including "zero")||Fixed (32-bit)||Condition register||Bi||MDMX, MIPS-3D||No||No|
|Nios II||32||200x||3||Register–Register||RISC||32||Fixed (32-bit)||Condition register||Little||Soft processor that can be instantiated on an Altera FPGA device||No||On Altera/Intel FPGA only|
|NS320xx||32||1982||5||Memory–Memory||CISC||8||Variable Huffman coded, up to 23 bytes long||Condition code||Little||BitBlt instructions|
|OpenRISC||32, 64||1.3||2010||3||Register–Register||RISC||16 or 32||Fixed||?||?||?||Yes||Yes|
|64 (32→64)||2.0||1986||3||Register–Register||RISC||32||Fixed (32-bit)||Compare and branch||Big → Bi||MAX||No|
1 multiplier quotient register
|Fixed (12-bit)||Condition register
Test and branch
|EAE (Extended Arithmetic Element)|
|PDP-11||16||1970||3||Memory–Memory||CISC||8 (includes stack pointer,
though any register can
act as stack pointer)
|Fixed (16-bit)||Condition code||Little||Floating Point,
Commercial Instruction Set
|POWER, PowerPC, Power ISA||32/64 (32→64)||3.1||1990||3||Register–Register||RISC||32||Fixed (32-bit), Variable (32- or 64-bit with the 32-bit prefix)||Condition code||Big/Bi||AltiVec, APU, VSX, Cell||Yes||Yes|
|RISC-V||32, 64, 128||20191213||2010||3||Register–Register||RISC||32 (including "zero")||Variable||Compare and branch||Little||?||Yes||Yes|
|RX||64/32/16||2000||3||Memory–Memory||CISC||4 integer + 4 address||Variable||Compare and branch||Little||No|
|SPARC||64 (32→64)||OSA2017||1985||3||Register–Register||RISC||32 (including "zero")||Fixed (32-bit)||Condition code||Big → Bi||VIS||Yes||Yes|
|RISC||16||Fixed (16- or 32-bit), Variable||Condition code
|64 (32→64)||1964||2 (most)
3 (FMA, distinct
4 (some vector inst.)
16 control (S/370 and later)
16 access (ESA/370 and later)
|Variable (16-, 32-, or 48-bit)||Condition code, compare and branch||Big||No||No|
|Transputer||32 (4→64)||1987||1||Stack machine||MISC||3 (as stack)||Variable (8 ~ 120 bytes)||Compare and branch||Little|
|VAX||32||1977||6||Memory–Memory||CISC||16||Variable||Compare and branch||Little||No|
|Z80||8||1976||2||Register–Memory||CISC||17||Variable (8 to 32 bits)||Condition register||Little|
|Instruction encoding||Branch evaluation||Endian-
- The LEA (all processors) and IMUL-immediate (80186 & later) instructions accept three operands; most other instructions of the base integer ISA accept no more than two operands.
- partly RISC: load/store architecture and simple addressing modes, partly CISC: three instruction lengths and no single instruction timing
- Since memory is an array of 60-bit words with no means to access sub-units, big endian vs. little endian makes no sense. The optional CMU unit uses big-endian semantics.
- Since memory is an array of 12-bit words with no means to access sub-units, big endian vs. little endian makes no sense.
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