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Comparison of instruction set architectures




In the early decades, there were computers that used binary, decimal and even ternary. Contemporary computers are almost exclusively binary.


Computer architectures are often described as n-bit architectures. Today n is often 8, 16, 32, or 64, but other sizes have been used. This is actually a strong simplification. A computer architecture often has a few more or less "natural" datasizes in the instruction set, but the hardware implementation of these may be very different. Many architectures have instructions operating on half and/or twice the size of respective processors' major internal datapaths. Examples of this are the 8080, Z80, MC68000 as well as many others. On this type of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The external databus width is often not useful to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses. The NS32764 had a 64-bit bus, but used 32-bit registers.

The width of addresses may or may not be different from the width of data. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.


The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture will allow

A := B + C

to be computed in one instruction.

A two-operand architecture will allow

A := A + B

to be computed in one instruction, so two instructions will need to be executed to simulate a single three-operand instruction

A := B
A := A + C


An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big endian architectures instead order them with the most significant byte at the lowest-numbered address. The x86 architecture as well as several 8-bit architectures are little endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big endian (ARM was little endian), but many (including ARM) are now configurable.

Endianness only applies to processors that allow individual addressing of units of data (such as bytes) that are smaller than the basic addressable machine word.

Instruction setsEdit

Usually the number of registers is a power of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of register files of architectures, mostly to simplify indexing modes. This table only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program pointer (PC). Those are not counted unless mentioned. Note that some architectures, such as SPARC, have register window; for those architectures, the count below indicates how many registers are available within a register window. Also, non-architected registers for register renaming are not counted.

Note, a common type of architecture, "load-store", is a synonym for "Register Register" below, meaning no instructions access memory except special – load to register(s) – and store from register(s) – with the possible exceptions of atomic memory operations for locking.

The table below compares basic information about instruction sets to be implemented in the CPU architectures:

Bits Version Intro-
Max #
Type Design Registers
(excluding FP/vector)
Instruction encoding Branch evaluation Endian-
Extensions Open Royalty
6502 8 1975 1 Register Memory CISC 3 Variable (8- to 32-bit) Condition register Little
65k 64 (8→64)[1] 2006? 1 Memory Memory
[citation needed]
CISC 1 Variable (8-bit to 256 bytes) Compare and branch
[citation needed]
68000 / 680x0 32 1979 2 Register Memory CISC 8 data and 8 address Variable Condition register Big
8080 8 1974 2 Register Memory CISC 8 Variable (8 to 24 bits) Condition register Little
8051 32 (8→32) 1977? 1 Register Register CISC
  • 32 in 4-bit
  • 16 in 8-bit
  • 8 in 16-bit
  • 4 in 32-bit
Variable (8-bit to 128 bytes) Compare and branch Little
8086 / x86 16, 32, 64
1978 2 (integer)
3 (AVX)[2]
Register Memory CISC
  • 8 (+ 4 or 6 segment reg.) (16/32-bit)
  • 16 (+ 2 segment reg. gs/cs) (64-bit)
Variable (8086: 8- to 48-bit) Condition code Little x87, IA-32, MMX, 3DNow!, SSE,
SSE2, PAE, x86-64, SSE3, SSE4,
No No
Alpha 64 1992 3 Register Register RISC 32 (including "zero") Fixed (32-bit) Condition register Bi MVI, BWX, FIX, CIX No
ARC 16/32 ARCv2[3] 1996 3 Register Register RISC 16 or 32 including SP
user can increase to 60
Variable (16- and 32-bit) Compare and branch Bi APEX User-defined instructions
ARM 32/16 ARMv7 and
1983 3 Register Register RISC
  • 7 in 16-bit thumb mode
  • 15 in 32-bit
Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2:
Variable (16- and 32-bit)
Condition code Bi NEON, Jazelle, VFP,
TrustZone, LPAE
ARMv8-A 64/32 ARMv8-A[4] 2011[5] 3 Register Register RISC 32 (including the stack pointer/"zero" register) Fixed (32-bit). In ARMv7 compatibility mode: Thumb:
Fixed (16-bit), Thumb-2: Variable (16- and 32-bit), A64
Condition code Bi none: all ARMv7
extensions are non-optional
AVR 8 1997 2 Register Register RISC 32
16 on "reduced architecture"
Variable (mostly 16-bit, four instructions are 32-bit) Condition register,
skip conditioned
on an I/O or
general purpose
register bit,
compare and skip
AVR32 32 Rev 2 2006 2–3 RISC 15 Variable[6] Big Java Virtual Machine
Blackfin 32 2000 RISC[7] 8 Little[8]
CDC Cyber 60 1970s 3 Register Memory RISC 24 (8 18-bit address reg.,
8 18-bit index reg.,
8 60-bit operand reg.)
Variable (15, 30, and 60-bit) Compare and branch n/a[9] Compare/Move Unit, additional
Peripheral Processing Units
No No
(native VLIW)
32[10] 2000 1 Register Register[10] VLIW[10][11]
  • 1 in native push stack mode
  • 6 in x86 emulation +
    8 in x87/MMX mode +
    50 in rename status
  • 12 integer + 48 shadow +
    4 debug in native VLIW
  • mode[10][11]
Variable (64- or 128-bit)[11] Condition code[10] Little
(native VLIW)
64 Elbrus-4S 2014 1 Register Register[10] VLIW 8-64 64 Condition code Little Just-in-time dynamic trans-
lation: x87, IA-32, MMX, SSE,
SSE2, x86-64, SSE3, AVX
No No
DLX 32 1990 3 RISC 32 Fixed (32-bit) Big
eSi-RISC 16/32 2009 3 Register Register RISC 8–72 Variable (16- or 32-bit) Compare and branch
and condition register
Bi User-defined instructions No No
64 2001 Register Register EPIC 128 Fixed (128 bit bundles with 5 bit template tag
and 3 instructions, each 41 bit long)
Condition register Bi
Intel Virtualization Technology No No
M32R 32 1997 RISC 16 Fixed (16- or 32-bit) Bi
Mico32 32 2006 3 Register Register RISC 32[12] Fixed (32-bit) Compare and branch Big User-defined instructions Yes[13] Yes
MIPS 64 (32→64) 5 1981 1–3 Register Register RISC 4–32 (including "zero") Fixed (32-bit) Condition register Bi MDMX, MIPS-3D Yes Yes[14]
MMIX 64 1999 3 Register Register RISC 256 Fixed (32-bit) Big Yes Yes
NS320xx 32 1982 5 Memory Memory CISC 8 Variable Huffman coded, up to 23 bytes long Condition code Little BitBlt instructions
OpenRISC 32, 64 2010 3 Register Register RISC 16 or 32 Fixed Yes Yes
64 (32→64) 2.0 1986 3 Register Register RISC 32 Fixed (32-bit) Compare and branch Big → Bi MAX No
PDP-11 16 1970–1990 3 Memory Memory CISC 8 (includes stack pointer,
though any register can
act as stack pointer)
Fixed (16) Condition code Little Floating Point,
Commercial Instruction Set
No No
PowerPC 32/64 (32→64) 2.07[15] 1991 3 Register Register RISC 32 Fixed (32-bit), Variable Condition code Big/Bi AltiVec, APU, VSX, Cell Yes No
RISC-V 32, 64, 128 2010 Register Register RISC 32 (including "zero") Variable Compare and branch Little Yes Yes
RX 64/32/16 2000 3 Memory Memory CISC 4 integer + 4 address Variable Compare and branch Little No
S+core 16/32 2005 RISC Little
SPARC 64 (32→64) OSA2017[16] 1985 3 Register Register RISC 32 (including "zero") Fixed (32-bit) Condition code Big → Bi VIS Yes Yes[17]
SuperH (SH) 32 1990s 2 Register Register
Register Memory
RISC 16 Fixed (16- or 32-bit), Variable Condition code
(single bit)
64 (32→64) 1964 2 (most)
3 (FMA, distinct
operand facility)

4 (some vector inst.)
Register Memory
Memory Memory
Register Register
CISC 16 Variable (16-, 32-, or 48-bit) Condition code, compare and branch Big No No
Transputer 32 (4→64) 1987 1 Stack machine MISC 3 (as stack) Variable (8 ~ 120 bytes) Compare and branch Little
VAX 32 1977 6 Memory Memory CISC 16 Variable Compare and branch Little
Z80 8 1976 2 Register Memory CISC 17 Variable (8 to 32 bits) Condition register Little
Bits Version Intro-
Max #
Type Design Registers
(excluding FP/vector)
Instruction encoding Branch evaluation Endian-
Extensions Open Royalty

See alsoEdit


  1. ^ "The 65k Project". Advanced 6502. Retrieved 20 December 2013.
  2. ^ The LEA (8086 & later) and IMUL-immediate (80186 & later) instructions accept three operands; most other instructions of the base integer ISA accept no more than two operands.
  3. ^
  4. ^ ARMv8 Technology Preview
  5. ^ "ARM goes 64-bit with new ARMv8 chip architecture". Retrieved 26 May 2012.
  6. ^ "AVR32 Architecture Document" (PDF). Atmel. Retrieved 2008-06-15.
  7. ^ "Blackfin Processor Architecture Overview". Analog Devices. Retrieved 2009-05-10.
  8. ^ "Blackfin memory architecture". Analog Devices. Retrieved 2009-12-18.
  9. ^ Since memory is an array of 60-bit words with no means to access sub-units, big endian vs. little endian makes no sense. The optional CMU unit uses big endian semantics.
  10. ^ a b c d e f "Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies.
  11. ^ a b c Alexander Klaiber (January 2000). "The Technology Behind Crusoe Processors" (PDF). Transmeta Corporation. Retrieved December 6, 2013.
  12. ^ "LatticeMico32 Architecture". Lattice Semiconductor. Retrieved 2009-12-18.
  13. ^ "Open Source Licensing". Lattice Semiconductor. Retrieved 2009-12-18.
  14. ^ The MIPS Open initiative
  15. ^ "Power ISA 2.07". IBM. Retrieved 2013-08-12.
  16. ^ Oracle SPARC Processor Documentation
  17. ^ SPARC Architecture License