An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost (among other things); because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.
An ISA defines everything a machine language programmer needs to know in order to program a computer. What an ISA defines differs between ISAs; in general, ISAs define the supported data types, what state there is (such as the main memory and registers) and their semantics (such as the memory consistency and addressing modes), the instruction set (the set of machine instructions that comprises a computer's machine language), and the input/output model.
Computer architectures are often described as n-bit architectures. In the 20th century, n is often 8, 16, or 32, and in the 21st century, n is often 16, 32 or 64, but other sizes have been used (including 6, 12, 18, 24, 30, 36, 39, 48, 60, 128). This is actually a simplification as computer architecture often has a few more or less "natural" data sizes in the instruction set, but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are the Z80, MC68000, and the IBM System/360. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as the IBM System/360 Model 30, have smaller internal data paths, while others, such as the 360/195, have larger internal data paths. The external databus width is not used to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses; the NS32764 had a 64-bit bus, and used 32-bit register. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.
The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture (2-in, 1-out) will allow
A := B + C
to be computed in one instruction
A two-operand architecture (1-in, 1-in-and-out) will allow
A := A + B
to be computed in one instruction, so two instructions will need to be executed to simulate a single three-operand instruction.
A := B A := A + C
Encoding length Edit
As can be seen in the table below some instructions sets keep to a very simple fixed encoding length, and other have variable-length. Usually it is RISC architectures that have fixed encoding length and CISC architectures that have variable length, but not always.
An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little-endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big-endian architectures instead arrange bytes with the most significant byte at the lowest-numbered address. The x86 architecture as well as several 8-bit architectures are little-endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big-endian (ARM was little-endian), but many (including ARM) are now configurable as either.
Endianness only applies to processors that allow individual addressing of units of data (such as bytes) that are smaller than the basic addressable machine word.
Instruction sets Edit
This section may be confusing or unclear to readers. In particular, Open and Royalty free are not defined and most entries are unsourced. (October 2021)
The table below compares basic information about instruction set architectures.
- Usually the number of registers is a power of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of register files of architectures, mostly to simplify indexing modes. The column "Registers" only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program counter (PC). Those are not counted unless mentioned. Note that some architectures, such as SPARC, have register windows; for those architectures, the count indicates how many registers are available within a register window. Also, non-architected registers for register renaming are not counted.
- In the "Type" column, "Register–Register" is a synonym for a common type of architecture, "load–store", meaning that no instruction can directly access memory except some special ones, i.e. load to or store from register(s), with the possible exceptions of memory locking instructions for atomic operations.
- In the "Endianness" column, "Bi" means that the endianness is configurable.
|Instruction encoding||Branch evaluation||Endian-
|6502||8||1975||1||Register–Memory||CISC||3||Variable (8- to 24-bit)||Condition register||Little|
|6800||8||1974||1||Register–Memory||CISC||3||Variable (8- to 32-bit)||Condition register||Big|
|6809||8||1978||1||Register–Memory||CISC||3||Variable (8- to 32-bit)||Condition register||Big|
|680x0||32||1979||2||Register–Memory||CISC||8 data and 8 address||Variable||Condition register||Big|
|8080||8||1974||2||Register–Memory||CISC||7||Variable (8 to 24 bits)||Condition register||Little|
||Variable (8-bit to 128 bytes)||Compare and branch||Little|
|x86||16, 32, 64
4 (FMA4 and
||Variable (8086 ~ 80386: variable between 1 and 6 bytes /w MMU + intel SDK, 80486: 2 to 5 bytes with prefix, pentium and onward: 2 to 4 bytes with prefix, x64: 4 bytes prefix, third party x86 emulation: 1 to 15 bytes w/o prefix & MMU . SSE/MMX: 4 bytes /w prefix AVX: 8 Bytes /w prefix)||Condition code||Little||x87, IA-32, MMX, 3DNow!, SSE,
SSE2, PAE, x86-64, SSE3, SSSE3, SSE4,
BMI, AVX, AES, FMA, XOP, F16C
|Alpha||64||1992||3||Register–Register||RISC||32 (including "zero")||Fixed (32-bit)||Condition register||Bi||MVI, BWX, FIX, CIX||No|
|ARC||16/32/64 (32→64)||ARCv3||1996||3||Register–Register||RISC||16 or 32 including SP
user can increase to 60
|Variable (16- or 32-bit)||Compare and branch||Bi||APEX User-defined instructions|
||Fixed (32-bit)||Condition code||Bi||NEON, Jazelle, VFP,
||Thumb: Fixed (16-bit), Thumb-2:
Variable (16- or 32-bit)
|Condition code||Bi||NEON, Jazelle, VFP,
|Arm64/A64||64||ARMv8-A||2011||3||Register–Register||RISC||32 (including the stack pointer/"zero" register)||Fixed (32-bit), Variable (32-bit or 64-bit for FMA4 with 32-bit prefix)||Condition code||Bi||SVE and SVE2||No|
16 on "reduced architecture"
|Variable (mostly 16-bit, four instructions are 32-bit)||Condition register,
on an I/O or
compare and skip
|AVR32||32||Rev 2||2006||2–3||RISC||15||Variable||Big||Java virtual machine|
8 data registers
8 pointer registers
4 index registers
4 buffer registers
|Variable (16- or 32-bit)||Condition code||Little|
|CDC Upper 3000 series||48||1963||3||Register–Memory||CISC||48-bit A reg., 48-bit Q reg., 6 15-bit B registers, miscellaneous||Variable (24- or 48-bit)||Multiple types of jump and skip||Big|
Central Processor (CP)
|60||1964||3||Register–Register||n/a[b]||24 (8 18-bit address reg.,
8 18-bit index reg.,
8 60-bit operand reg.)
|Variable (15-, 30-, or 60-bit)||Compare and branch||n/a[c]||Compare/Move Unit||No||No|
Peripheral Processor (PP)
|12||1964||1 or 2||Register–Memory||CISC||1 18-bit A register, locations 1–63 serve as index registers for some instructions||Variable (12- or 24-bit)||Test A register, test channel||n/a[d]||additional Peripheral Processing Units||No||No|
|32||2000||1||Register–Register||VLIW||Variable (64- or 128-bit in native mode, 15 bytes in x86 emulation)||Condition code||Little|
|64||Elbrus-4S||2014||1||Register–Register||VLIW||8–64||64||Condition code||Little||Just-in-time dynamic translation: x87, IA-32, MMX, SSE,
SSE2, x86-64, SSE3, AVX
|eSi-RISC||16/32||2009||3||Register–Register||RISC||8–72||Variable (16- or 32-bit)||Compare and branch
and condition register
|iAPX 432||32||1981||3||Stack machine||CISC||0||Variable (6 to 321 bits)||No||No|
|64||2001||Register–Register||EPIC||128||Fixed (128-bit bundles with 5-bit template tag and 3 instructions, each 41-bit long)||Condition register||Bi
|Intel Virtualization Technology||No||No|
|LoongArch||32, 64||2021||4||Register–Register||RISC||32 (including "zero")||Fixed (32-bit)||Little||No||No|
|M32R||32||1997||3||Register–Register||RISC||16||Variable (16- or 32-bit)||Condition register||Bi|
|Mico32||32||?||2006||3||Register–Register||RISC||32||Fixed (32-bit)||Compare and branch||Big||User-defined instructions||Yes||Yes|
|MIPS||64 (32→64)||6||1981||1–3||Register–Register||RISC||4–32 (including "zero")||Fixed (32-bit)||Condition register||Bi||MDMX, MIPS-3D||No||No|
|Nios II||32||2000||3||Register–Register||RISC||32||Fixed (32-bit)||Condition register||Little||Soft processor that can be instantiated on an Altera FPGA device||No||On Altera/Intel FPGA only|
|NS320xx||32||1982||5||Memory–Memory||CISC||8||Variable Huffman coded, up to 23 bytes long||Condition code||Little||BitBlt instructions|
|OpenRISC||32, 64||1.3||2000||3||Register–Register||RISC||16 or 32||Fixed||?||?||?||Yes||Yes|
|64 (32→64)||2.0||1986||3||Register–Register||RISC||32||Fixed (32-bit)||Compare and branch||Big → Bi||MAX||No|
1 multiplier quotient register
|Fixed (12-bit)||Condition register
Test and branch
|EAE (Extended Arithmetic Element)|
|PDP-11||16||1970||2||Memory–Memory||CISC||8 (includes program counter and stack pointer, though any register can act as stack pointer)||Variable (16-, 32-, or 48-bit)||Condition code||Little||Floating Point,
Commercial Instruction Set
|POWER, PowerPC, Power ISA||32/64 (32→64)||3.1||1990||3 (mostly). FMA, LD/ST-Update||Register–Register||RISC||32 GPR, 8 4-bit Condition Fields, Link Register, Counter Register||Fixed (32-bit), Variable (32- or 64-bit with the 32-bit prefix)||Condition code, Branch-Counter auto-decrement||Bi-endian||AltiVec, APU, VSX, Cell, Floating-point, Matrix Mutiply Assist||Yes||Yes|
|RISC-V||32, 64, 128||20191213||2010||3||Register–Register||RISC||32 (including "zero")||Variable||Compare and branch||Little||?||Yes||Yes|
|RX||64/32/16||2000||3||Memory–Memory||CISC||4 integer + 4 address||Variable||Compare and branch||Little||No|
|SPARC||64 (32→64)||OSA2017||1985||3||Register–Register||RISC||32 (including "zero")||Fixed (32-bit)||Condition code||Big → Bi||VIS||Yes||Yes|
|RISC||16||Fixed (16- or 32-bit), Variable||Condition code
|64 (32→64)||1964||2 (most)
3 (FMA, distinct
4 (some vector inst.)
16 control (S/370 and later)
16 access (ESA/370 and later)
|Variable (16-, 32-, or 48-bit)||Condition code, compare and branch auto increment, Branch-Counter auto-decrement||Big||No||No|
|Transputer||32 (4→64)||1987||1||Stack machine||MISC||3 (as stack)||Variable (8 ~ 120 bytes)||Compare and branch||Little|
|VAX||32||1977||6||Memory–Memory||CISC||16||Variable||Condition code, compare and branch||Little||No|
|Z80||8||1976||2||Register–Memory||CISC||17||Variable (8 to 32 bits)||Condition register||Little|
|Instruction encoding||Branch evaluation||Endian-
See also Edit
- The LEA (all processors) and IMUL-immediate (80186 & later) instructions accept three operands; most other instructions of the base integer ISA accept no more than two operands.
- partly RISC: load/store architecture and simple addressing modes, partly CISC: three instruction lengths and no single instruction timing
- Since memory is an array of 60-bit words with no means to access sub-units, big endian vs. little endian makes no sense. The optional CMU unit uses big-endian semantics.
- Since memory is an array of 12-bit words with no means to access sub-units, big endian vs. little endian makes no sense.
- da Cruz, Frank (October 18, 2004). "The IBM Naval Ordnance Research Calculator". Columbia University Computing History. Retrieved January 28, 2019.
- "Russian Virtual Computer Museum – Hall of Fame – Nikolay Petrovich Brusentsov".
- Trogemann, Georg; Nitussov, Alexander Y.; Ernst, Wolfgang (2001). Computing in Russia: the history of computer devices and information technology revealed. Vieweg+Teubner Verlag. pp. 19, 55, 57, 91, 104–107. ISBN 978-3-528-05757-2..
- "AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions" (PDF). AMD. November 2009.
- "Synopsys Introduces New 64-bit ARC Processor IP Delivering up to 3x Performance Increase for High-End Embedded Applications".
- "ARMv8 Technology Preview" (PDF). Archived from the original (PDF) on 2018-06-10. Retrieved 2011-10-28.
- "ARM goes 64-bit with new ARMv8 chip architecture". 27 October 2011. Retrieved 26 May 2012.
- "Hot Chips 30 conference; Fujitsu briefing" (PDF). Toshio Yoshida. Archived from the original (PDF) on 2020-12-05.
- "AVR32 Architecture Document" (PDF). Atmel. Retrieved 2008-06-15.
- "Blackfin manual" (PDF). analog.com.
- "Blackfin Processor Architecture Overview". Analog Devices. Retrieved 2009-05-10.
- "Blackfin memory architecture". Analog Devices. Archived from the original on 2011-06-16. Retrieved 2009-12-18.
- "Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies.
- Alexander Klaiber (January 2000). "The Technology Behind Crusoe Processors" (PDF). Transmeta Corporation. Retrieved December 6, 2013.
- Intel Corporation (1981). Introduction to the iAPX 432 Architecture (PDF). pp. iii.
- "LatticeMico32 Architecture". Lattice Semiconductor. Archived from the original on 23 June 2010.
- "LatticeMico32 Open Source Licensing". Lattice Semiconductor. Archived from the original on 20 June 2010.
- MIPS64 Architecture for Programmers: Release 6
- MIPS32 Architecture for Programmers: Release 6
- MIPS Open
- "Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning".
- OpenRISC Architecture Revisions
- "PDP-8 Users Handbook" (PDF). bitsavers.org. 2019-02-16.
- "Power ISA Version 3.1". openpowerfoundation.org. 2020-05-01. Retrieved 2021-10-20.
- "RISC-V ISA Specifications". Retrieved 17 June 2019.
- Oracle SPARC Processor Documentation
- SPARC Architecture License