AES instruction set
An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed (as well as the resistance to side-channel attacks) of applications performing encryption and decryption using Advanced Encryption Standard (AES). They are often implemented as instructions implementing a single round of AES along with a special version for the last round which has a slightly different method.
x86 architecture processorsEdit
AES-NI (or the Intel Advanced Encryption Standard New Instructions; AES-NI) was the first major implementation. AES-NI is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008.
||Perform one round of an AES encryption flow|
||Perform the last round of an AES encryption flow|
||Perform one round of an AES decryption flow|
||Perform the last round of an AES decryption flow|
||Assist in AES round key generation[note 1]|
||Assist in AES Inverse Mix Columns|
- Westmere based processors, specifically:
- Sandy Bridge processors:
- Ivy Bridge processors
- All i5, i7, Xeon and i3-2115C only
- Haswell processors (all except i3-4000m, Pentium and Celeron)
- Broadwell processors (all except Pentium and Celeron)
- Silvermont/Airmont processors (all except Bay Trail-D and Bay Trail-M)
- Goldmont (and later) processors
- Skylake (and later) processors
Several AMD processors support AES instructions:
Hardware acceleration in other architecturesEdit
AES support with unprivileged processor instructions is also available in the latest SPARC processors (T3, T4, T5, M5, and forward) and in latest ARM processors. The SPARC T4 processor, introduced in 2011, has user-level instructions implementing AES rounds. These instructions are in addition to higher level encryption commands. The ARMv8-A processor architecture, announced in 2011, including the ARM Cortex-A53 and A57 (but not previous v7 processors like the Cortex A5, 7, 8, 9, 11, 15) also have user-level instructions which implement AES rounds. In August 2012, IBM announced that the then-forthcoming Power7+ architecture would have AES support. The commands in these architectures are not directly equivalent to the AES-NI commands, but implement similar functionality.
IBM z9 or later mainframe processors support AES as single-opcode (KM, KMC) AES ECB/CBC instructions via IBM's CryptoExpress hardware. These single-instruction AES versions are therefore easier to use than Intel NI ones, but may not be extended to implement other algorithms based on AES round functions (such as the Whirlpool and Grøstl hash functions).
Supporting x86 CPUsEdit
The following chips, while supporting AES hardware acceleration, do not support AES-NI:
- AMD Geode LX processors
- VIA, using VIA PadLock
Programming information is available in ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile (Section A2.3 "The Armv8 Cryptographic Extension").
- ARMv8-A architecture
- ARM cryptographic extensions optionally supported on ARM Cortex-A30/50/70 cores
- Cryptographic hardware accelerators/engines
- Atmel XMEGA (on-chip accelerator with parallel execution, not an instruction)
- SPARC T3 and later processors have hardware support for several cryptographic algorithms, including AES.
- Cavium Octeon MIPS All Cavium Octeon MIPS-based processors have hardware support for several cryptographic algorithms, including AES using special coprocessor 3 instructions.
In AES-NI Performance Analyzed, Patrick Schmid and Achim Roos found "impressive results from a handful of applications already optimized to take advantage of Intel's AES-NI capability". A performance analysis using the Crypto++ security library showed an increase in throughput from approximately 28.0 cycles per byte to 3.5 cycles per byte with AES/GCM versus a Pentium 4 with no acceleration.‹See TfM›[failed verification][better source needed]
Most modern compilers can emit AES instructions.
Much security and cryptography software supports the AES instruction set, including the following core infrastructure:
- Apple's FileVault 2 full-disk encryption in macOS 10.10+
- NonStop SSH2, NonStop cF SSL Library and BackBox VTC Software in HPE Tandem NonStop OS L-series
- Cryptography API: Next Generation (CNG) (requires Windows 7)
- Linux's Crypto API
- Java 7 HotSpot
- Network Security Services (NSS) version 3.13 and above (used by Firefox and Google Chrome)
- Solaris Cryptographic Framework on Solaris 10 onwards
- FreeBSD's OpenCrypto API (aesni(4) driver)
- OpenSSL 1.0.1 and above
- FLAM/FLUC 5.1.08 (released 2015-08-24) and above
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- "Some products can support AES New Instructions with a Processor Configuration update, in particular, i7-2630QM/i7-2635QM, i7-2670QM/i7-2675QM, i5-2430M/i5-2435M, i5-2410M/i5-2415M. Please contact OEM for the BIOS that includes the latest Processor configuration update".
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- "Intel Core i3-4000M Processor (3M Cache, 2.40 GHz) Product Specifications".
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- Intel Advanced Encryption Standard Instructions (AES-NI)
- AES instruction set whitepaper (2.93 MiB, PDF) from Intel