Bit Manipulation Instruction Sets
Bit Manipulation Instructions Sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions in these sets are non-SIMD and operate only on general-purpose registers.
There are two sets published by Intel: BMI (here referred to as BMI1) and BMI2; they were both introduced with the Haswell microarchitecture. Another two sets were published by AMD: ABM (Advanced Bit Manipulation, which is also a subset of SSE4a implemented by Intel as part of SSE4.2 and BMI1), and TBM (Trailing Bit Manipulation, an extension introduced with Piledriver-based processors as an extension to BMI1, but dropped again in Zen-based processors).
ABM (Advanced Bit Manipulation)Edit
ABM is only implemented as a single instruction set by AMD; all AMD processors support both instructions or neither. Intel considers
POPCNT as part of SSE4.2, and
LZCNT as part of BMI1.
POPCNT has a separate CPUID flag; however, Intel uses AMD's
ABM flag to indicate
LZCNT support (since
LZCNT completes the ABM).
||Leading zeros count|
LZCNT is almost identical to the Bit Scan Reverse (
BSR) instruction, but sets the ZF (if the result is zero) and CF (if the source is zero) flags rather than OF, and produces a defined result (the source operand size in bits) if the source operand is zero.
BMI1 (Bit Manipulation Instruction Set 1)Edit
The instructions below are those enabled by the
BMI bit in CPUID. Intel officially considers
LZCNT as part of BMI, but advertises
LZCNT support using the
ABM CPUID feature flag. BMI1 is available in AMD's Jaguar, Piledriver and newer processors, and in Intel's Haswell and newer processors.
|Instruction||Description||Equivalent C expression|
||Logical and not||~x & y|
||Bit field extract (with register)||(src >> start) & ((1 << len) - 1)|
||Extract lowest set isolated bit||x & -x|
||Get mask up to lowest set bit||x ^ (x - 1)|
||Reset lowest set bit||x & (x - 1)|
||Count the number of trailing zero bits||N/A|
BMI2 (Bit Manipulation Instruction Set 2)Edit
Intel introduced BMI2 together with BMI1 in its line of Haswell processors. Only AMD has produced processors supporting only BMI1 without BMI2; BMI2 is supported by AMDs Excavator architecture and newer.
||Zero high bits starting with specified bit position|
||Unsigned multiply without affecting flags, and arbitrary destination registers|
||Parallel bits deposit|
||Parallel bits extract|
||Rotate right logical without affecting flags|
||Shift arithmetic right without affecting flags|
||Shift logical right without affecting flags|
||Shift logical left without affecting flags|
Parallel bit deposit and extractEdit
PEXT instructions are new generalized bit-level compress and expand instructions. They take two inputs; one is a source, and the other is a selector. The selector is a bitmap selecting the bits that are to be packed or unpacked.
PEXT copies selected bits from the source to contiguous low-order bits of the destination; higher-order destination bits are cleared.
PDEP does the opposite for the selected bits: contiguous low-order bits are copied to selected bits of the destination; other destination bits are cleared. This can be used to extract any bitfield of the input, and even do a lot of bit-level shuffling that previously would have been expensive. While what these instructions do is similar to a bit level gather-scatter SIMD instructions,
PEXT instructions (like the rest of the BMI instruction sets) operate on general-purpose registers.
Below are a few 16-bit examples of these operations:
|Input||Selector example||Parallel bit extract||Parallel bit deposit|
TBM (Trailing Bit Manipulation)Edit
TBM consists of instructions complementary to the instruction set started by BMI1; their complementary nature means they do not necessarily need to be used directly but can be generated by an optimizing compiler when supported. AMD introduced TBM together with BMI1 in its Piledriver line of processors; AMD Jaguar and Zen-based processors do not support TBM.
|Instruction||Description||Equivalent C expression|
||Bit field extract (with immediate)||(src >> start) & ((1 << len) - 1)|
||Fill from lowest clear bit||x & (x + 1)|
||Isolate lowest clear bit||x | ~(x + 1)|
||Isolate lowest clear bit and complement||~x & (x + 1)|
||Mask from lowest clear bit||x ^ (x + 1)|
||Set lowest clear bit||x | (x + 1)|
||Fill from lowest set bit||x | (x - 1)|
||Isolate lowest set bit and complement||~x | (x - 1)|
||Inverse mask from trailing ones||~x | (x + 1)|
||Mask from trailing zeros||~x & (x - 1)|
- K10-based processors (ABM supported)
- "Cat" low-power processors
- "Heavy Equipment" processors
- Zen-based processors (ABM, BMI1 and BMI2 supported)
- Zen+-based processors (ABM, BMI1 and BMI2 supported)
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- "Family 16h AMD A-Series Data Sheet" (PDF). amd.com. AMD. October 2013. Retrieved 2014-01-02.
- Hollingsworth, Brent. "New "Bulldozer" and "Piledriver" instructions" (pdf). Advanced Micro Devices, Inc. Retrieved 11 December 2014.
- Locktyukhin, Max. "How to detect New Instruction support in the 4th generation Intel® Core™ processor family". www.intel.com. Intel. Retrieved 11 December 2014.
- "bmiintrin.h from GCC 4.8". Retrieved 2014-03-17.
- "Chess Programming BMI1". Retrieved 2014-04-08.
- "AMD Excavator Core May Bring Dramatic Performance Increases". X-bit labs. October 18, 2013. Archived from the original on October 23, 2013. Retrieved November 24, 2013.
- "chessprogramming - BMI2". Retrieved 2014-02-09.
- Yedidya Hilewitz; Ruby B. Lee (August 2009). "A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations" (PDF). palms.princeton.edu. IEEE Transactions on Computers. pp. 1035–1048. Retrieved 2014-02-10.
- "chessprogramming - TBM". Retrieved 2014-02-09.
- "tbmintrin.h from GCC 4.8". Retrieved 2014-03-17.
- "BIOS and Kernel Developer's Guide for AMD Family 14h" (PDF). Retrieved 2014-01-03.