The Puma Family 16h is a low-power microarchitecture by AMD for its APUs. It succeeds the Jaguar as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h. The Beema line of processors are aimed at low-power notebooks, and Mullins are targeting the tablet sector.
|Max. CPU clock rate||1.35 GHz to 2.5 GHz|
|L1 cache||64 KB per core|
|L2 cache||1 MB to 2 MB shared|
|Architecture and classification|
|Min. feature size||28 nm|
|Instruction set||AMD64 (x86-64)|
|GPU(s)||Radeon Rx: 128 cores, 300–800 Mhz|
|Products, models, variants|
|Predecessor||Jaguar - Family 16h|
The Puma cores use the same microarchitecture as Jaguar, and inherits the design:
- Out-of-order execution and Speculative execution, up to 4 CPU cores
- Two-way integer execution
- Two-way 128-bit wide floating-point and packed integer execution
- Integer hardware divider
- Puma does not feature clustered multi-thread (CMT), meaning that there are no "modules"
- Puma does not feature Heterogeneous System Architecture or zero-copy
- 32 KiB instruction + 32 KiB data L1 cache per core
- 1–2 MiB unified L2 cache shared by two or four cores
- Integrated single channel memory controller supporting 64bit DDR3L
- 3.1 mm2 area per core
Instruction set supportEdit
Like Jaguar, the Puma core has support for the following instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and AMD-V.
- 19% CPU core leakage reduction at 1.2V
- 38% GPU leakage reduction
- 500 mW reduction in memory controller power
- 200 mW reduction in display interface power
- Chassis temperature aware turbo boost
- Selective boosting according to application needs (intelligent boost)
- Support for ARM TrustZone via integrated Cortex-A5 processor
- Support for DDR3L-1866 memory
AMD released a revision of Puma core, Puma+, as a part of the Carrizo-L platform in 2015. The differences in the CPU microarchitecture are unclear. Puma+ featured 2 or 4 cores up to 2.5GHz and required the newer FP4 socket.
Features and ASICsEdit
- APU models: A8-7680, A6-7480. CPU only: Athlon X4 845.
- Unified shaders : texture mapping units : render output units
- To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
- To feed more than two displays, the additional panels must have native DisplayPort support. Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
- DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.
|Cores||Frequency||Max. Turbo||L2 Cache||Model||Config.||Max. Freq.|
|A8||6410||Socket FT3b||4||2.0GHz||2.4 GHz||2 MB||Radeon R5||128:?:?||800 MHz||15 W||DDR3L-1866|
|A6||6310||1.8GHz||Radeon R4||800 MHz|
|A4||6250J||2.0GHz||N/A||Radeon R3||600 MHz||25 W||DDR3L-1600|
|A4||6210||1.8GHz||Radeon R3||600 MHz||15 W|
|E2||6110||1.5GHz||Radeon R2||500 MHz|
|E1||6010||2||1.35 GHz||1 MB||350 MHz||10 W||DDR3L-1333|
|Cores||Frequency||Max. Turbo||L2 Cache||Model||Config.||Max. Freq.||TDP||SDP|
|A10 Micro||6700T||4||1.2 GHz||2.2 GHz||2 MB||Radeon R6||128:?:?||500 MHz||4.5 W||2.8 W||DDR3L-1333|
|A6 Micro||6500T||1.8 GHz||Radeon R4||401 MHz|
|A4 Micro||6400T||1.0 GHz||1.6 GHz||Radeon R3||350 MHz|
|E1 Micro||6200T||2||1.4 GHz||1 MB||Radeon R2||300 MHz||3.95 W||DDR3L-1066|
- "Software Optimization Guide for Family 16h Processors". AMD. Retrieved August 3, 2013.
- "AMD launches new Beema, Mullins SoCs". ExtremeTech. 2014-04-29. Retrieved 2014-05-02.
- Shimpi, Anand. "AMD Beema/Mullins Architecture & Performance Preview". AnandTech. Retrieved 29 April 2014.
- Shimpi, Anand. "New Turbo Boost, The Lineup and Trustzone". AnandTech. Retrieved 29 April 2014.
- Woligroski, Don. "Meet The Mullins And Beema Tablet APUs". Toms Hardware. Retrieved 29 April 2014.
- Cutress, Ian (12 May 2015). "AMD's Carrizo-L APU Unveiled". Anandtech. Retrieved 14 January 2017.
- "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
- "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
- "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
- Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
- Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
- Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
- "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
- "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
- Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
- "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
- Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
- Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
- Software Optimization Guide for Family 16h Processors
- 2014 AMD Low-Power Mobile APUs
- Jaguar presentation (video) at ISSCC 2013
- Discussion initiated on RWT forums by Jeff Rupley, Chief Architect of the Jaguar core
- BKDG for Family 16h Models 00h-0Fh Processors
- Revision Guide for Family 16h Models 00h-0Fh Processors (Jaguar)
- Revision Guide for Family 16h Models 30h-3Fh Processors (Puma)