AMD Excavator Family 15h is a microarchitecture developed by AMD to succeed Steamroller Family 15h for use in AMD APU processors and normal CPUs. On October 12, 2011, AMD revealed Excavator to be the code name for the fourth-generation Bulldozer-derived core.
|Architecture and classification|
|Min. feature size||28 nm bulk silicon (GF28A)|
|Instruction set||AMD64 (x86-64)|
|Products, models, variants|
|Predecessor||Steamroller – Family 15h (3rd-gen)|
The Excavator-based APU for mainstream applications is called Carrizo and was released in 2015. The Carrizo APU is designed to be HSA 1.0 compliant. An Excavator-based APU and CPU variant named Toronto for server and enterprise markets was also produced.
Excavator was the final revision of the "Bulldozer" family, with two new microarchitectures replacing Excavator a year later. Excavator was succeeded by the x86-64 Zen architecture in early 2017.
Excavator added hardware support for new instructions such as AVX2, BMI2 and RDRAND. Excavator is designed using High Density (aka "Thin") Libraries normally used for GPUs to reduce electric energy consumption and die size, delivering a 30 percent increase in efficient energy use. Excavator can process up to 15% more instructions per clock compared to AMD's previous core Steamroller.
Features and ASICsEdit
|Desktop||Mainstream||Carrizo||Bristol Ridge||Raven Ridge||Picasso|
|Mainstream||Llano||Trinity||Richland||Kaveri||Carrizo||Bristol Ridge||Raven Ridge||Picasso|
|Basic||Desna, Ontario, Zacate||Kabini, Temash||Beema, Mullins||Carrizo-L||Stoney Ridge|
|Embedded||Trinity||Bald Eagle||Merlin Falcon,
|Great Horned Owl||Ontario, Zacate||Kabini||Steppe Eagle, Crowned Eagle,
|Prairie Falcon||Banded Kestrel|
|Platform||High, standard and low power||Low and ultra-low power|
|Released||Aug 2011||Oct 2012||Jun 2013||Jan 2014||Jun 2015||Jun 2016||Oct 2017||Jan 2019||2020||Jan 2011||May 2013||Apr 2014||May 2015||Feb 2016||Apr 2019|
|CPU microarchitecture||K10||Piledriver||Steamroller||Excavator||"Excavator+"||Zen||Zen+||Zen 2||Bobcat||Jaguar||Puma||Puma+||"Excavator+"||Zen|
|PCI Express version||2.0||3.0||2.0||3.0|
|Fab. (nm)||GF 32SHP
|die area (mm2)||228||246||245||245||250||210||149||75 (+ 28 FCH)||107||?||125|
|Max APU TDP||100W||95W||65W||65W||45W||18W||25W|
|Max stock APU base clock (GHz)||3||3.8||4.1||3.7||3.8||3.6||3.7||3||1.75||2.2||2||2.2||3.2||3.3|
|Max APUs per node[b]||1||1|
|Max CPU[c] cores per APU||4||8||2||4||2|
|Max threads per CPU core||1||2||1||2|
|i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF|
|BMI1, AES-NI, CLMUL, and F16C||N/A|
|AVIC, BMI2 and RDRAND||N/A||N/A|
|ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO||N/A||N/A|
|WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT||N/A||N/A|
|FPUs per core||1||0.5||1||1||0.5||1|
|Pipes per FPU||2||2|
|FPU pipe width||128-bit||256-bit||80-bit||128-bit|
|CPU instruction set SIMD level||SSE4a[e]||AVX||AVX2||SSSE3||AVX||AVX2|
|FMA4, LWP, TBM, and XOP||N/A||N/A||N/A||N/A|
|L1 data cache per core (KiB)||64||16||32||32|
|L1 data cache associativity (ways)||2||4||8||8|
|L1 instruction caches per core||1||0.5||1||1||0.5||1|
|Max APU total L1 instruction cache (KiB)||256||128||192||256||64||128||96||128|
|L1 instruction cache associativity (ways)||2||3||4||8||2||3||4|
|L2 caches per core||1||0.5||1||1||0.5||1|
|Max APU total L2 cache (MiB)||4||2||4||1||2||1|
|L2 cache associativity (ways)||16||8||16||8|
|APU total L3 cache (MiB)||N/A||4||8||N/A||4|
|APU L3 cache associativity (ways)||16||16|
|L3 cache scheme||victim||N/A||victim||victim|
|Max stock DRAM support||DDR3-1866||DDR3-2133||DDR3-2133, DDR4-2400||DDR4-2400||DDR4-2933||DDR4-3200, LPDDR4-4266||DDR3L-1333||DDR3L-1600||DDR3L-1866||DDR3-1866, DDR4-2400||DDR4-2400|
|Max DRAM channels per APU||2||1||2|
|Max stock DRAM bandwidth (GB/s) per APU||29.866||34.132||38.400||46.932||68.256||10.666||12.800||14.933||19.200||38.400|
|GPU microarchitecture||TeraScale 2 (VLIW5)||TeraScale 3 (VLIW4)||GCN 2nd gen||GCN 3rd gen||GCN 5th gen||TeraScale 2 (VLIW5)||GCN 2nd gen||GCN 3rd gen||GCN 5th gen|
|GPU instruction set||TeraScale instruction set||GCN instruction set||TeraScale instruction set||GCN instruction set|
|Max stock GPU base clock (MHz)||600||800||844||866||1108||1250||1400||1750||538||600||?||847||900||1100|
|Max stock GPU base GFLOPS[f]||480||614.4||648.1||886.7||1134.5||1760||1971.2||1792||86||?||?||?||345.6||460.8|
|3D engine[g]||Up to 400:20:8||Up to 384:24:6||Up to 512:32:8||Up to 704:44:16||Up to 512:?:?||80:8:4||128:8:4||Up to 192:?:?||Up to 192:?:?|
|Video decoder||UVD 3.0||UVD 4.2||UVD 6.0||VCN 1.0||UVD 3.0||UVD 4.0||UVD 4.2||UVD 6.0||UVD 6.3||VCN 1.0|
|Video encoder||N/A||VCE 1.0||VCE 2.0||VCE 3.1||N/A||VCE 2.0||VCE 3.1|
|GPU power saving||PowerPlay||PowerTune||PowerPlay||PowerTune|
|PlayReady[h]||N/A||3.0 not yet||N/A||3.0 not yet|
|Supported displays[i]||2–3||2–4||3||3 (desktop)
4 (mobile, embedded)
- APU models: A8-7680, A6-7480. CPU only: Athlon X4 845.
- A PC would be one node.
- An APU combines a CPU and a GPU. Both have cores.
- Requires firmware support.
- No SSE4. No SSSE3.
- Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
- Unified shaders : texture mapping units : render output units
- To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
- To feed more than two displays, the additional panels must have native DisplayPort support. Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
- DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.
There are three APU lines announced or released:
- Budget and mainstream markets (desktop and mobile): Carrizo APU
- The Carrizo mobile APUs were launched in 2015 based on Excavator x86 cores and featuring Heterogeneous System Architecture for integrated task sharing between CPUs and GPUs, which allows a GPU to perform compute functions, which is claimed provide greater performance increases than shrinking the feature size alone.
- Carrizo desktop APUs were launched in 2018. The mainsream product (A8-7680) has 4 Excavator cores and a GPU based on GCN1.2 architecture. Also, an entry-level APU (A6-7480) with 2 Excavator cores is also launched.
- Budget and mainstream markets (desktop and mobile): Bristol Ridge, and Stoney Ridge (for entry level notebooks), APUs
- Enterprise and server markets: Toronto APU
- The Toronto APU for server and enterprise markets featured four x86 Excavator CPU core modules and Volcanic Islands integrated GPU core.
- The Excavator cores has a greater advantage with IPC than Steamroller. The improvement is 4–15%.
- Support for HSA/hUMA, DDR3/DDR4, PCIe 3.0, GCN 1.2
- The Toronto APU was available in BGA and SoC variants. The SoC variant had the southbridge on the same die as the APU to save space and power and to optimize workloads.
- A complete system with a Toronto APU would have a maximum power usage of 70 W.
CPU Desktop linesEdit
Excavator CPU for Desktop announced on 2nd Feb 2016, named Athlon X4 845.In 2017, three more desktop CPUs(Athlon X4 9x0) were launched. They come in Socket AM4, with a TDP of 65W. In fact, they are APUs with their graphics cores disabled.
|CPU model||Frequency (GHz)||Cores||TDP (Watt)||Socket||L1D cache||L2 cache||PCI Express 3.0||Relative IPC||Locked|
|Athlon X4 845 (Carrizo)||3.5 (3.8 turbo)||4||65||Socket FM2+ (906)||4*32KB||2*1MB||X8||1.0||Yes|
|Athlon X4 940 (Bristol Ridge)||3.2 (3.6 turbo)||4||65||Socket AM4 (1331)||4*32KB||2*1MB||X16||1.1||No|
|Athlon X4 950 (Bristol Ridge)||3.5 (3.8 turbo)||4||65||Socket AM4 (1331)||4*32KB||2*1MB||X16||1.1||No|
|Athlon X4 970 (Bristol Ridge)||3.8 (4.0 turbo)||4||65||Socket AM4 (1331)||4*32KB||2*1MB||X16||1.1||No|
The AMD Opteron roadmaps for 2015 show the Excavator-based Toronto APU and Toronto CPU intended for 1 Processor (1P) cluster applications:
- For 1P Web and Enterprise Services Clusters:
- Toronto CPU – quad-core x86 Excavator architecture
- plans for Cambridge CPU – 64-bit AArch64 core
- For 1P Compute and Media Clusters:
- Toronto APU – quad-core x86 Excavator architecture
- For 2P/4P Servers:
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- Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
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