MOS Technology 6502
The MOS Technology 6502 (typically "sixty-five-oh-two" or "six-five-oh-two") is an 8-bit microprocessor that was designed by a small team led by Chuck Peddle for MOS Technology. When it was introduced in 1975, the 6502 was, by a considerable margin, the least expensive full-featured microprocessor on the market. It initially sold for less than one-sixth the cost of competing designs from larger companies, such as Motorola and Intel, and caused rapid decreases in pricing across the entire processor market. Along with the Zilog Z80, it sparked a series of projects that resulted in the home computer revolution of the early 1980s.
A MOS 6502 processor in a DIP-40 plastic package. The four-digit date code indicates it was made in the 45th week of 1985
|Max. CPU clock rate||1 MHz to 3 MHz|
|Instruction set||MOS 6502|
Popular home video game consoles and computers, such as the Atari 2600, Atari 8-bit family, Apple II, Nintendo Entertainment System, Commodore 64, and others, used the 6502 or variations of the basic design. Soon after the 6502's introduction, MOS Technology was purchased outright by Commodore International, who continued to sell the microprocessor and licenses to other manufacturers. In the early days of the 6502, it was second-sourced by Rockwell and Synertek, and later licensed to other companies. In its CMOS form, which was developed by the Western Design Center, the 6502 family continues to be widely used in embedded systems, with estimated production volumes in the hundreds of millions.
History and useEdit
Origins at MotorolaEdit
The 6502 was designed by many of the same engineers that had designed the Motorola 6800 microprocessor family. Motorola started the 6800 microprocessor project in 1971 with Tom Bennett as the main architect. The chip layout began in late 1972, the first 6800 chips were fabricated in February 1974 and the full family was officially released in November 1974. John Buchanan was the designer of the 6800 chip and Rod Orgill, who later did the 6501, assisted Buchanan with circuit analyses and chip layout. Bill Mensch joined Motorola in June 1971 after graduating from the University of Arizona (at age 26). His first assignment was helping define the peripheral ICs for the 6800 family and later he was the principal designer of the 6820 Peripheral Interface Adapter (PIA). Motorola's engineers could run analog and digital simulations on an IBM 370-165 mainframe computer. Bennett hired Chuck Peddle in 1973 to do architectural support work on the 6800 family products already in progress. He contributed in many areas, including the design of the 6850 ACIA (serial interface).
Motorola's target customers were established electronics companies such as Hewlett-Packard, Tektronix, TRW and Chrysler. In May 1972, Motorola's engineers began visiting select customers and sharing the details of their proposed 8-bit microprocessor system with ROM, RAM, parallel and serial interfaces. In early 1974, they provided engineering samples of the chips so that customers could prototype their designs. Motorola's "total product family" strategy did not focus on the price of the microprocessor, but on reducing the customer's total design cost. They offered development software on a timeshare computer, the "EXORciser" system debugging system, onsite training and field application engineer support. Both Intel and Motorola had initially announced a $360 price for a single microprocessor. (The IBM System/360 mainframe was a well known computer at the time.) The actual price for production quantities was much less. Motorola offered a design kit containing the 6800 with six support chips for $300.
Peddle, who would accompany the sales people on customer visits, found that customers were put off by the high cost of the microprocessor chips. To lower the price, the IC chip size would have to shrink so that more chips could be produced on each silicon wafer. This could be done by removing inessential features in the 6800 and using a newer fabrication technology, "depletion-mode" MOS transistors. Peddle and other team members started outlining the design of an improved feature, reduced size microprocessor. At that time, Motorola's new semiconductor fabrication facility in Austin, Texas was having difficulty producing MOS chips and mid 1974 was the beginning of a year-long recession in the semiconductor industry. Also, many of the Mesa, Arizona employees were displeased with the upcoming relocation to Austin. Motorola Semiconductor Products Division's management was overwhelmed with problems and showed no interest in Peddle's low-cost microprocessor proposal. Chuck Peddle was frustrated with Motorola's management for missing this new opportunity. In a November 1975 interview, Motorola's Chairman, Robert Galvin, agreed. He said, "We did not choose the right leaders in the Semiconductor Products division." The division was reorganized and the management replaced. New group vice-president John Welty said, "The semiconductor sales organization lost its sensitivity to customer needs and couldn't make speedy decisions."
Peddle began looking for a source of funding for this new project and found a small semiconductor company in Pennsylvania. In August 1974, Chuck Peddle, Bill Mensch, Rod Orgill, Harry Bawcum, Ray Hirt, Terry Holdt and Wil Mathys left Motorola to join MOS Technology. (Mike James joined later.) Of the seventeen chip designers and layout people on the 6800 team, seven left. There were 30 to 40 other marketers, application engineers and system engineers on the 6800 team. That December, Gary Daniels transferred into the 6800 microprocessor group. Tom Bennett did not want to leave the Phoenix area so Daniels took over the microprocessor development in Austin. His first project was a "depletion-mode" version of the 6800; this cut the chip area nearly in half and doubled the speed. The faster parts were available in July 1976. This was followed by the 6802 which added 128 bytes of RAM and an on-chip clock oscillator circuit.
Moving to MOS TechnologyEdit
MOS Technology was formed in 1969 by three executives from General Instrument, Mort Jaffe, Don McLaughlin, and John Pavinen, to produce metal-oxide-semiconductor (MOS) integrated circuits. Allen-Bradley, a supplier of electronic components and industrial controls, acquired a majority interest in 1970. The company designed and fabricated custom ICs for customers and had developed a line of calculator chips.
On August 19, 1974, the former Motorola employees moved into MOS Technology's headquarters at Valley Forge, Pennsylvania. The goal was to design and produce a low cost microprocessor for embedded applications and to target as wide as possible a customer base. This would only be possible if the microprocessor was low cost—and in the semiconductor business, chip size determined cost. The size goal required n-channel "depletion-mode" MOS transistors, a more advanced process than MOS Technology's calculator chips used. John Pavinen was able to have the fabrication process ready by June 1975. Chuck Peddle, Rod Orgill, and Wil Mathys designed the initial architecture of the new processors. There would be two microprocessors: the 6501 would plug into the same socket as the Motorola 6800, while the 6502 would work with 6800 family peripherals and have an on-chip clock oscillator. These processors would not run 6800 software because they had a different instruction set, different registers, and mostly different addressing modes. A September 1975 article in EDN magazine gives this summary of the design:
The MOS Technology 650X family represents a conscious attempt of eight former Motorola employees who worked on the development of the 6800 system to put out a part that would replace and outperform the 6800, yet undersell it. With the benefit of hindsight gained on the 6800 project, the MOS Technology team headed by Chuck Peddle, made the following architectural changes in the Motorola CPU…
The second "B" accumulator was omitted. The 16-bit 6800 index register was split into two 8-bit registers and these registers operate in the "true" indexing mode. Three-state control was eliminated from the address bus outputs. A clock generator was included on the chip. The address bus was always active so the VMA (valid-memory address) output was eliminated. An "8080-type" RDY signal for single-cycle stepping was added.
The chip high level design had to be turned into drawings of transistors and interconnects. At MOS Technology, the "layout" was a very manual process done with color pencils and vellum paper. The layout consisted of thousands of polygon shapes on six different drawings; one for each layer of the semiconductor fabrication process. Rod Orgill was responsible for the 6501 design; he had assisted John Buchanan at Motorola on the 6800. Bill Mensch did the 6502; he was the designer of the 6820 Peripheral Interface Adapter (PIA) at Motorola. Harry Bawcom, Mike James and Sydney-Anne Holt helped with the layout.
The size goal for the 6502 chip was 153 x 168 mils (3.9 x 4.3 mm) or an area of 16.6 mm2. At that time the technical literature would state the length and width of each chip in "mils" (0.001 inch). The original 6800 chips were 212 x 212 mils (5.4 x 5.4 mm) or an area of 29.0 mm2. A smaller area means more chips per silicon wafer and makes each of those smaller chips less likely to be fabricated with a defect (since the tiny defects generally are randomly and uniformly distributed over the wafer area: each finished wafer will generally have about the same number of defects, so the more chips on the wafer, the smaller the ratio of chips with defects to chips overall). The first layouts did not reach their target size. The first 6502 chips were 168 x 183 mils (4.3 x 4.7 mm) or an area of 19.8 mm2. The Rotate Right instruction (ROR) did not work in the first silicon, so the instruction was temporarily omitted from the published documents, but the next iteration of the design shrank the chip and fixed the Rotate Right instruction, which was then included in revised documentation.
Introducing the 6501 and 6502Edit
MOS Technology's microprocessor introduction was quite different from the traditional months-long product launch. The first run of a new integrated circuit is normally used for internal testing and shared with select customers as "engineering samples". These chips often have a minor design defect or two that will be corrected before production begins. Chuck Peddle's goal was to sell the first run 6501 and 6502 chips to the attendees at the Wescon trade show in San Francisco beginning on September 16, 1975. Peddle was a very effective spokesman and the MOS Technology microprocessors were extensively covered in the trade press. One of the earliest was a full-page story on the MCS6501 and MCS6502 microprocessors in the July 24, 1975 issue of Electronics magazine. Stories also ran in EE Times (August 24, 1975), EDN (September 20, 1975), Electronic News (November 3, 1975), Byte (November 1975) and Microcomputer Digest (November 1975). Advertisements for the 6501 appeared in several publications the first week of August 1975. The 6501 would be for sale at Wescon for $20 each. In September 1975, the advertisements included both the 6501 and the 6502 microprocessors. The 6502 would cost only $25.
When MOS Technology arrived at Wescon, they found that exhibitors could not sell anything on the show floor. They rented the MacArthur Suite at the St. Francis Hotel and directed customers there to purchase the processors. At the suite, the processors were stored in large jars to imply that the chips were in production and readily available. The customers did not know the bottom half of each jar contained non-functional chips. The chips were $20 and $25 while the documentation package was an additional $10. Users were encouraged to make copies of the documents, an inexpensive way for MOS Technology to distribute product information. The processors were supposed to have 56 instructions, but the Rotate Right (ROR) instruction did not work correctly on these chips, so the preliminary data sheets listed just 55 instructions. The reviews in Byte and EDN noted the lack of the ROR instruction. The next revision of the layout fixed this problem and the May 1976 datasheet listed 56 instructions. Peddle wanted every interested engineer and hobbyist to have access to the chips and documentation; other semiconductor companies only wanted to deal with "serious" customers. For example, Signetics was introducing the 2650 microprocessor and its advertisements asked readers to write for information on their company letterhead.
|3||∅1 (in)||∅1 (in)||∅1 (out)|
|5||Valid Memory Address||Valid Memory Address||N.C.|
|7||Bus Available||Bus Available||SYNC|
|36||Data Bus Enable||Data Bus Enable||N.C.|
|37||∅2 (in)||∅2 (in)||∅0 (in)|
|38||N.C.||N.C.||Set Overflow Flag|
|39||Three-State Control||N.C.||∅2 (out)|
The 6501/6502 introduction in print and at Wescon was an enormous success. The downside was that the extensive press coverage got Motorola's attention. In October 1975, Motorola reduced the price of a single 6800 microprocessor from $175 to $69. The $300 system design kit was reduced to $150 and it now came with a printed circuit board. On November 3, 1975, Motorola sought an injunction in Federal Court to stop MOS Technology from making and selling microprocessor products. They also filed a lawsuit claiming patent infringement and misappropriation of trade secrets. Motorola claimed that seven former employees joined MOS Technology to create that company's microprocessor products.
Motorola was a billion-dollar company with a plausible case and lawyers. On October 30, 1974, Motorola had filed numerous patent applications on the microprocessor family and was granted twenty-five patents. The first was in June 1976 and the second was to Bill Mensch on July 6, 1976 for the 6820 PIA chip layout. These patents covered the 6800 bus and how the peripheral chips interfaced with the microprocessor. Motorola began making transistors in 1950 and had a portfolio of semiconductor patents. Allen-Bradley decided not to fight this case and sold their interest in MOS Technology back to the founders. Four of the former Motorola engineers were named in the suit: Chuck Peddle, Will Mathys, Bill Mensch and Rod Orgill. All were named inventors in the 6800 patent applications. During the discovery process, Motorola found that one engineer, Mike James, had ignored Peddle's instructions and brought his 6800 design documents to MOS Technology. In March 1976, the now independent MOS Technology was running out of money and had to settle the case. They agreed to drop the 6501 processor, pay Motorola $200,000 and return the documents that Motorola contended were confidential. Both companies agreed to cross-license microprocessor patents. That May, Motorola dropped the price of a single 6800 microprocessor to $35. By November Commodore had acquired MOS Technology.
Computers and gamesEdit
With legal troubles behind them, MOS was still left with the problem of getting developers to try their processor, prompting Chuck Peddle to design the MDT-650 ("microcomputer development terminal") single-board computer. Another group inside the company designed the KIM-1, which was sold semi-complete and could be turned into a usable system with the addition of a 3rd party computer terminal and compact cassette drive. Much to their amazement, the KIM-1 sold well to hobbyists and tinkerers, as well as to the engineers to which it had been targeted. The related Rockwell AIM 65 control/training/development system also did well. The software in the AIM 65 was based on that in the MDT. Another roughly similar product was the Synertek SYM-1.
One of the first "public" uses for the design was the Apple I microcomputer, introduced in 1976. The 6502 was next used in the Commodore PET and the Apple II, both released in 1977. It was later used in the Atari and Acorn Atom home computers, the BBC Micro family, the Commodore VIC-20 and a large number of other designs both for home computers and business, such as Ohio Scientific and Oric. The 6510, a direct successor of the 6502 with a digital I/O port and a tri-state address bus, was the CPU utilized in the best-selling Commodore 64 home computer. Commodore's floppy disk drive, the 1541, had a processor of its own—it too was a 6502.
Another important use of the 6500 family was in video games. The first to make use of the processor design was the Atari 2600 video game console. The 2600 used an offshoot of the 6502 called the 6507, which had fewer pins and, as a result, could address only 8 KB of memory. Millions of the Atari consoles would be sold, each with a MOS processor. Another significant use was by the Nintendo Entertainment System and Famicom. The 6502 used in the NES was a second source version by Ricoh, a partial system-on-a-chip, that lacked the binary-coded decimal mode but added 22 memory-mapped registers (and on-die hardware) for sound generation, joypad reading, and sprite list DMA. Called 2A03 in NTSC consoles and 2A07 in PAL consoles (the difference being the memory divider ratio and a lookup table for audio sample rates), this processor was produced exclusively for Nintendo.
In the 1980s, a popular electronics magazine Elektor/Elektuur used the processor in its microprocessor development board Junior Computer.
|MOS 6502 registers|
The 6502 is a little-endian 8-bit processor with a 16-bit address bus. The original versions were fabricated using an 8 µm process technology chip with an advertised die size of 153 x 168 mils (3.9 x 4.3 mm) or an area of 16.6 mm2.
The internal logic runs at the same speed as the external clock rate, but despite the slow clock speeds (typically in the neighborhood of 1 to 2 MHz), the 6502's performance was competitive with other contemporary CPUs using significantly faster clocks. This is partly due to a simplistic state machine implemented by combinatorial (clockless) logic to a greater extent than in many other designs; the two phase clock (supplying two synchronizations per cycle) can thereby control the whole machine-cycle directly. Typical instructions might take half as many cycles to complete on the 6502 than contemporary designs. Like most simple CPUs of the era, the dynamic NMOS 6502 chip is not sequenced by a microcode ROM but uses a PLA (which occupied about 15 percent of the chip area) for instruction decoding and sequencing. Like most eight-bit microprocessors, the chip does some limited overlapping of fetching and execution.
The low clock frequency moderated the speed requirement of memory and peripherals attached to the CPU, as only about 50 percent of the clock cycle was available for memory access (due to the asynchronous design, this percentage varied strongly among chip versions). This was critical at a time when affordable memory had access times in the range 250 - 450 ns. The original NMOS 6502 was minimalistically engineered and efficiently manufactured and therefore cheap—an important factor in getting design wins in the very price-sensitive game console and home computer markets. Like its precursor, the Motorola 6800, the 6502 has very few registers. At the time the processor was designed, the number of transistors that could be economically put on a chip was very constrained (around a few thousand), so it made sense to rely on RAM instead of allocating expensive NMOS chip area for CPU registers. To this end, the CPU includes a 'zero-page' addressing mode that uses one address byte in the instruction instead of the two needed to address the full 64 KB of memory. This provides fast access to the first 256 bytes of RAM by using shorter instructions. Chuck Peddle has said in interviews that the specific intention was to allow these first 256 bytes of RAM to be used like registers.
The 6502's registers include one 8-bit accumulator register (A), two 8-bit index registers (X and Y), 7 processor status flag bits (P), an 8-bit stack pointer (S), and a 16-bit program counter (PC). The stack's address space is hardwired to memory page $01, i.e. the address range $0100–$01FF (256–511). Software access to the stack is done via four implied addressing mode instructions, whose functions are to push or pop (pull) the accumulator or the processor status register. The same stack is also used for subroutine calls via the JSR (Jump to Subroutine) and RTS (Return from Subroutine) instructions and for interrupt handling.
The chip uses the index and stack registers effectively with several addressing modes, including a fast "direct page" or "zero page" mode, similar to that found on the PDP-8, that accesses memory locations from addresses 0 to 255 with a single 8-bit address (saving the cycle normally required to fetch the high-order byte of the address)—code for the 6502 uses the zero page much as code for other processors would use registers. On some 6502-based microcomputers with an operating system, the OS uses most of zero page, leaving only a handful of locations for the user.
Addressing modes also include implied (1 byte instructions); absolute (3 bytes); indexed absolute (3 bytes); indexed zero-page (2 bytes); relative (2 bytes); accumulator (1); indirect,x and indirect,y (2); and immediate (2). Absolute mode is a general-purpose mode. Branch instructions use a signed 8-bit offset relative to the instruction after the branch; the numerical range -128..127 therefore translates to 128 bytes backward and 127 bytes forward from the instruction following the branch (which is 126 bytes backward and 129 bytes forward from the start of the branch instruction). Accumulator mode uses the accumulator as an effective address, and does not need any operand data. Immediate mode uses an 8-bit literal operand.
The indirect modes are useful for array processing and other looping. With the 5/6 cycle "(indirect),y" mode, the 8-bit Y register is added to a 16-bit base address read from zero page which is located by a single byte following the opcode. The Y register is therefore an index-register in the sense that it is used to hold an actual index (as opposed to the X register in the 6800 where a base address was directly stored and to which an immediate offset could be added). Incrementing the index register to walk the array byte-wise takes only two additional cycles. With the less frequently used "(indirect,x)" mode the effective address for the operation is found at the zero page address formed by adding the second byte of the instruction to the contents of the X register. Using the indexed modes, the zero page effectively acts as a set of up to 128 additional (though very slow) address registers.
The 6502 is capable of performing addition and subtraction in binary or binary coded decimal. Placing the CPU into BCD mode with the SED (set D flag) instruction results in decimal arithmetic, in which $99 + $01 would result in $00 and the carry (C) flag being set. In binary mode (CLD, clear D flag), the same operation would result in $9A and the carry flag being cleared. Other than Atari BASIC, BCD mode was seldom used in home computer applications.
The processor's non-maskable interrupt (NMI) input is edge sensitive, which means that the interrupt is triggered by the falling edge of the signal rather than its level. The implication of this feature is that a wired-OR interrupt circuit is not readily supported. However, this also prevents nested NMI interrupts from occurring until the hardware makes the NMI input inactive again, often under control of the NMI interrupt handler.
The simultaneous assertion of the NMI and IRQ (maskable) hardware interrupt lines causes IRQ to be ignored. However, if the IRQ line remains asserted after the servicing of the NMI, the processor will immediately respond to IRQ, as IRQ is level sensitive. Thus a sort of built-in interrupt priority was established in the 6502 design.
The "Break" flag of the processor is very different from the other flag bits. It has no flag setting, resetting, or testing instructions of its own, and is not affected by the PHP and PLP instructions. It exists only on the stack, where BRK and PHP always write a 1, while IRQ and NMI always write a 0.
The "SO" input pin, when asserted, will set the processor's overflow status bit (deasserting it does not clear the overflow bit, however). This can be used by a high-speed polling device driver, which can poll the hardware once in only three cycles by using a Branch-on-oVerflow-Clear (BVC) instruction that branches to itself. For example, the Commodore 1541 and other Commodore floppy disk drives use this technique to detect without delay whether the serializer is ready to accept or provide another byte of disk data. Obviously great care must be used in the device driver and the associated system design, as spurious assertion of the overflow bit could ruin arithmetic processing.
Assembly language instructionsEdit
A 6502 assembly language statement consists of a three character instruction mnemonic, followed by an operand in the case of an instruction that takes an operand. When assembled, the resulting machine code will consist of a one byte operation code (opcode), followed by a one or two byte operand, if the instruction was assembled with an operand, hence 6502 machine instructions vary in length from one to three bytes. The operand will be stored in the 6502's customary little-endian format. The 65C816, the 16-bit CMOS version of the 6502, also supports 24 bit addressing, which addressing modes will result in instructions being assembled with three byte operands, also arranged in little-endian format.
|6502 INSTRUCTION SET OPCODE MATRIX|
|Addressing modes: A-accumulator, #-immediate, zpg-zero page, abs-absolute, ind-indirect, X-indexed by X-register, Y-indexed by Y-register, rel-relative|
|High Nibble||Low Nibble|
|0||BRK||ORA (ind,X)||ORA zpg||ASL zpg||PHP||ORA #||ASL A||ORA abs||ASL abs|
|1||BPL rel||ORA (ind),Y||ORA zpg,X||ASL zpg,X||CLC||ORA abs,Y||ORA abs,X||ASL abs,X|
|2||JSR abs||AND (ind,X)||BIT zpg||AND zpg||ROL zpg||PLP||AND #||ROL A||BIT abs||AND abs||ROL abs|
|3||BMI rel||AND (ind),Y||AND zpg,X||ROL zpg,X||SEC||AND abs,Y||AND abs,X||ROL abs,X|
|4||RTI||EOR (ind,X)||EOR zpg||LSR zpg||PHA||EOR #||LSR A||JMP abs||EOR abs||LSR abs|
|5||BVC rel||EOR (ind),Y||EOR zpg,X||LSR zpg,X||CLI||EOR abs,Y||EOR abs,X||LSR abs,X|
|6||RTS||ADC (ind,X)||ADC zpg||ROR zpg||PLA||ADC #||ROR A||JMP (ind)||ADC abs||ROR abs|
|7||BVS rel||ADC (ind),Y||ADC zpg,X||ROR zpg,X||SEI||ADC abs,Y||ADC abs,X||ROR abs,X|
|8||STA (ind,X)||STY zpg||STA zpg||STX zpg||DEY||TXA||STY abs||STA abs||STX abs|
|9||BCC rel||STA (ind),Y||STY zpg,X||STA zpg,X||STX zpg,Y||TYA||STA abs,Y||TXS||STA abs,X|
|A||LDY #||LDA (ind,X)||LDX #||LDY zpg||LDA zpg||LDX zpg||TAY||LDA #||TAX||LDY abs||LDA abs||LDX abs|
|B||BCS rel||LDA (ind),Y||LDY zpg,X||LDA zpg,X||LDX zpg,Y||CLV||LDA abs,Y||TSX||LDY abs,X||LDA abs,X||LDX abs,Y|
|C||CPY #||CMP (ind,X)||CPY zpg||CMP zpg||DEC zpg||INY||CMP #||DEX||CPY abs||CMP abs||DEC abs|
|D||BNE rel||CMP (ind),Y||CMP zpg,X||DEC zpg,X||CLD||CMP abs,Y||CMP abs,X||DEC abs,X|
|E||CPX #||SBC (ind,X)||CPX zpg||SBC zpg||INC zpg||INX||SBC #||NOP||CPX abs||SBC abs||INC abs|
|F||BEQ rel||SBC (ind),Y||SBC zpg,X||INC zpg,X||SED||SBC abs,Y||SBC abs,X||INC abs,X|
|Blank opcodes, e.g., F2, and all opcodes whose low nibbles are 3, 7, B and F are undefined in the 6502 instruction set.|
Variations and derivativesEdit
There were several variants of the NMOS 6502:
- The MOS Technology 6503 had reduced memory addressing capability (4 KB) and no RDY input, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and S.O. pins of the 6502 also omitted).
- The MOS Technology 6504 had reduced memory addressing capability (8 KB), no NMI, and no RDY input, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and S.O. pins of the 6502 also omitted).
- The MOS Technology 6505 had reduced memory addressing capability (4 KB) and no NMI, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and S.O. pins of the 6502 also omitted).
- The MOS Technology 6506 had reduced memory addressing capability (4 KB), no NMI, and no RDY input, but all 3 clock pins of the 6502 (i.e. a 2-phase output clock), in a 28-pin DIP package (with the SYNC, redundant Vss, and S.O. pins of the 6502 also omitted).
- The MOS Technology 6507 had reduced memory addressing capability (8 KB) and no interrupts, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and S.O. pins of the 6502 also omitted).
- The MOS Technology 6509 could address up to 1 MB of RAM as 16 banks of 64 kB and was used in the Commodore CBM-II series.
- The MOS Technology 6510 has a built-in 6-bit programmable input/output port and was used in the Commodore 64.
- The MOS Technology 6512 was a 6502 with a 2-phase clock input for an external clock oscillator, instead of an on-board clock oscillator.
- The MOS Technology 6513 was a 6503 with a 2-phase clock input like the 6512.
- The MOS Technology 6514 was a 6504 with a 2-phase clock input like the 6512.
- The MOS Technology 6515 was a 6505 with a 2-phase clock input like the 6512.
- The Ricoh 2A03 was a 6502 variant including an audio processing unit and lacking the BCD mode, used in the Nintendo Entertainment System.
- The 6502B clocked at 1.79 MHz was used in early Atari 8-bit computers.
- The 6502C (Sally) was a customized 6502 chip used in later Atari 8-bit computers. It has a HALT signal on pin 35 and a second R/W on pin 36 (these pin are N/C on a standard 6502).
- The 65C02 is a CMOS version of the NMOS 6502 that was designed by Bill Mensch of the Western Design Center, featuring reduced power consumption, support for much higher clock speeds, new instructions, new addressing modes for some existing instructions, and correction of NMOS errata, such as the JMP ($xxFF) bug.
- CSG 65CE02 was a CMOS derivative developed by the Commodore Semiconductor Group (CSG), formerly MOS Technology.
- The Rockwell R65F11 (introduced in 1983) and the later R65F12 are enhanced versions of the 6502-based processor, also including on-chip zero-page RAM, on-chip Forth kernel ROM, a UART, etc.
- The GTE G65SC102 is software compatible with the 65C02, but has a slightly different pinout and oscillator circuit. The BBC Master Turbo included the 4 MHz version of this CPU on a coprocessor card, which could also be bought separately and added to the Master 128.
- The Rockwell R65C00, R65C21, and R65C29 featured two enhanced CMOS 6502s in a single chip, and the R65C00 and R65C21 additionally contained 2 kB of mask-programmable ROM.
6512, 6513, 6514, & 6515Edit
The MOS Technology 6512, 6513, 6514, and 6515 each rely on an external clock, instead of using an internal clock generator like the 650x (e.g. 6502). This was used to advantage in some designs where the clocks could be run asymmetrically, increasing overall CPU performance.
The 6512 was used in the BBC Micro B+64.
The Western Design Center designed and currently produces the W65C816S processor, a 16-bit, static-core successor to the 65C02, with greatly enhanced features. The 65C816 powered the Apple IIGS computer, and was the basis of the Ricoh 5A22 processor that powered the popular Super Nintendo Entertainment System. The W65C816S is available through electronics distributors.
The Western Design Center also designed and produced the 65C802, which was a 65C816 core with a 64 KB address space in a 65(C)02 pin-compatible package. The 65C802 could be retrofitted to a 6502 board and would function as a 65C02 on power-up, operating in "emulation mode." As with the 65C816, a two-instruction sequence would switch the 65C802 to "native mode" operation, exposing its 16 bit accumulator and index registers, as well as other 65C816 enhanced features. The 65C802 was not widely used: new designs almost always were built around the 65C816, resulting in 65C802 production being discontinued.
The 65GZ032 designed by Gideon Zweijtzer is a VHDL source core that is 6502 compatible and extends the 8-bit CPU to a 32-bit design. It features pipelined RISC, new opcodes, access to 4 GByte of linear memory, paged memory and a clock speed of 33 MHz.
The following 6502 assembly language source code is for a subroutine named
TOLOWER, which copies a null-terminated character string from one location to another, converting upper case letter characters to lower case letters. The string being copied is the "source" and the string into which the converted source is stored is the "destination."
; TOLOWER: ; ; Convert a null-terminated character string to all lower case. ; Maximum string length is 255 characters, plus the null term- ; inator. ; ; Parameters: ; ; SRC - Source string address ; DST - Destination string address ; ORG $0080 ; 0080 00 04 SRC .WORD $0400 ;source string pointer ($40) 0082 00 05 DST .WORD $0500 ;destination string pointer ($42) ; 0600 ORG $0600 ;execution start address ; 0600 A0 00 TOLOWER LDY #$00 ;starting index ; 0602 B1 80 LOOP LDA (SRC),Y ;get from source string 0604 F0 11 BEQ DONE ;end of string ; 0606 C9 41 CMP #'A' ;if lower than UC alphabet... 0608 90 06 BCC SKIP ;copy unchanged ; 060A C9 5B CMP #'Z'+1 ;if greater than UC alphabet... 060C B0 02 BCS SKIP ;copy unchanged ; 060E 09 20 ORA #%00100000 ;convert to lower case ; 0610 91 82 SKIP STA (DST),Y ;store to destination string 0612 C8 INY ;bump index 0613 D0 ED BNE LOOP ;next character ; ; NOTE: If .Y wraps the destination string will be left in an undefined ; state. We set carry to indicate this to the calling function. ; 0615 38 SEC ;report string too long error &... 0616 60 RTS ;return to caller ; 0617 91 82 DONE STA (DST),Y ;terminate destination string 0618 18 CLC ;report conversion completed &... 0619 60 RTS ;return to caller ; .END
Bugs and quirksEdit
- The earliest revisions of the 6502, such as those shipped with some KIM-1 computers, had a severe bug in the ROR (rotate right memory or accumulator) instruction. The operation of ROR in these chips is effectively an ASL instruction that does not affect the carry bit in the status register. MOS left the instruction out of chip documentation entirely because of the defect, promising that ROR would appear on 6502 chips starting in 1976. The vast majority of 6502 chips in existence today do not exhibit this bug.
- The NMOS 6502 family has a variety of undocumented instructions, which vary from one chip manufacturer to the next. The 6502's instruction decoding is implemented in a hardwired logic array (similar to a programmable logic array) that is only defined for 151 of the 256 available opcodes. The remaining 105 trigger strange and occasionally hard-to-predict actions, such as crashing the processor, performing two valid instructions consecutively, performing strange mixtures of two instructions, or simply doing nothing at all. Eastern House Software developed the "Trap65", a device that plugged between the processor and its socket to convert (trap) unimplemented opcodes into BRK (software interrupt) instructions. Some programmers utilized this feature to extend the 6502's instruction set by providing functionality for the unimplemented opcodes with specially written software intercepted at the BRK instruction's 0xFFFE vector. All of the undefined opcodes have been replaced by NOP instructions in the 65C02, an enhanced CMOS version of the 6502, although with varying byte sizes and execution times. In the 65C802/65C816, all 256 opcodes perform defined operations.
- The 6502's memory indirect jump instruction, JMP (<address>), is partially broken. If <address> is hex xxFF (i.e., any word ending in FF), the processor will not jump to the address stored in xxFF and xxFF+1 as expected, but rather the one defined by xxFF and xx00 (for example, JMP ($10FF) would jump to the address stored in 10FF and 1000, instead of the one stored in 10FF and 1100). This defect continued through the entire NMOS line, but was corrected in the CMOS derivatives.
- The NMOS 6502's indexed addressing across page boundaries will do an extra read of an invalid address. This characteristic may cause random issues by accessing hardware that acts on a read, such as clearing timer or IRQ flags, sending an I/O handshake, etc. This defect continued through the entire NMOS line, but was corrected in the CMOS derivatives, in which the processor does an extra read of the last instruction byte.
- The 6502's read-modify-write instructions perform one read and two write cycles. First the unmodified data that was read is written back, and then the modified data is written. This characteristic may cause issues by twice accessing hardware that acts on a write. This anomaly continued through the entire NMOS line, but was fixed in the CMOS derivatives, in which the processor will do two reads and one write cycle. Good programming practice will generally avoid this problem by not executing read/modify/write instructions on hardware registers.
- The N (result negative), V (sign bit overflow) and Z (result zero) status flags are generally meaningless when performing arithmetic operations while the processor is in BCD mode, as these flags reflect the binary, not BCD, result. This limitation was removed in the CMOS derivatives. Therefore, this feature may be used to distinguish a CMOS processor from an NMOS version.
- If the processor happens to be in BCD mode when a hardware interrupt occurs it will not revert to binary mode. This characteristic could result in obscure bugs in the interrupt service routine if it fails to clear BCD mode before performing any arithmetic operations. For example, the Commodore 64's KERNAL did not correctly handle this processor characteristic, requiring that IRQs be disabled or re-vectored during BCD math operations. This issue was addressed in the CMOS derivatives as well.
- The 6502 instruction set includes BRK (opcode $00), which is technically a software interrupt (similar in spirit to the SWI mnemonic of the 6800 and ARM processors). BRK is most often used to interrupt program execution and start a machine language monitor for testing and debugging during software development. BRK could also be used to route program execution using a simple jump table (analogous to the manner in which the 8086 and derivatives handle software interrupts by number). Unfortunately, if a hardware interrupt occurs at the same time the processor is fetching a BRK instruction, the NMOS version of the processor will fail to execute BRK and instead proceed as if only a hardware interrupt had occurred. This fault was corrected in the CMOS implementation of the processor.
- When executing JSR (jump to subroutine) and RTS (return from subroutine) instructions, the return address pushed to the stack by JSR is that of the last byte of the JSR operand (that is, the most significant byte of the subroutine address), rather than the address of the following instruction. This is because the actual copy (from program counter to stack and then vice versa) takes place before the automatic increment of the program counter that occurs at the end of every instruction. This characteristic would go unnoticed unless the code examined the return address in order to retrieve parameters in the code stream (a 6502 programming idiom documented in the ProDOS 8 Technical Reference Manual). It remains a characteristic of 6502 derivatives to this day.
As the 6502 is externally clocked, upgrading the speed involves more than dropping a faster chip into the processor socket; many other components also need to be modified. To meet user demand, a number of companies sold hardware to speed up those systems. These "accelerators" included a modicum of high-speed RAM and glue circuitry used to synchronize the faster processor with the computer's original RAM and its peripherals. For example, the Apple II floppy disk relied on software accessing the controller's I/O registers with critical timing; Apple II accelerators were therefore designed to fall back to 1 MHz during disk access. The first accelerators were circuit boards; some later accelerators (such as the Zip Chip) miniaturized the processor and support circuits to fit into a DIP package that was plug compatible with the original processor.
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- Bagnall (2010), p. 11. Peddle's new offer came at an opportune time for the 6800 developers. "They didn't want to go to Austin, Texas," explains Mensch.
- Waller, Larry (November 13, 1975). "Motorola seeks to end skid". Electronics. New York: McGraw-Hill. 48 (23): 96–98. Summary: Semiconductor Products split into two parts, integrated circuits and discrete components. Semiconductor losses for the last four quarters exceeded $30 million. The sales organization lost its sensitivity to customer needs, "delays in responding to price cuts meant that customers bought elsewhere." Technical problems plagued IC production. The troubles are "not in design, but in chip and die yields." Problems have been solved. The MC6800 microprocessor "arrived in November 1974."
- Motorola 6800 Oral History (2008), p. 13
- "Electronics Newsletter: 6800 gains speed, lower prices by summer". Electronics. New York: McGraw-Hill. 49 (5): 25. March 4, 1976.
- Daniels, R. Gary (December 1996). "A Participant’s Perspective". IEEE Micro. IEEE Computer Society. 16 (5): 21–31. doi:10.1109/40.546562. Daniels, "My first assignment was to lead a small team to redesign the 6800 MPU to make it more manufacturable and so that higher speed versions could be selected."
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- Bagnall (2010), p. 19 "Paivinen promised Peddle he would have the n-channel process ready. He was true to his word."
- Stanford University, Silicon Genesis project: videotaped oral history interview of Willam Mensch
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- Motorola 6800 Oral History (2008), p. 10
- The August 1975 datasheet had 55 instructions with no ROR, the May 1976 datasheet had the ROR and 56 instructions. File:MCS650x Instruction Set.jpg
- "Microprocessor line offers 4, 8,16 bits". Electronics. New York: McGraw-Hill. 48 (15): 118. July 24, 1975. The article covers the 6501 and 6502 plus the 28 pin versions that would only address 4K of memory. It also covered future devices such as "a design that Peddle calls a pseudo 16".
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- Motorola was awarded the following US Patents on the 6800 microprocessor family: 3962682, 3968478, 3975712, 3979730, 3979732, 3987418, 4003028, 4004281, 4004283, 4006457, 4010448, 4016546, 4020472, 4030079, 4032896, 4037204, 4040035, 4069510, 4071887, 4086627, 4087855, 4090236, 4145751, 4218740, 4263650.
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- Bagnall (2010), pp. 55-56
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The first 6502 was fabricated with 8 micron technology, ran at one megahertz and had a maximum memory of 64k.
- 6502 Instruction Set
- NMOS 6502 Opcodes
- 1982 MOS Technology Data Catalog (pdf obtained from bitsavers.org)
- Randy M. Dumse. "The R65F11 and F68K Single-Chip Forth Computers". [permanent dead link]  1984.
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- Rockwell. "RSC-Forth User's Manual". 1983.
- "Advanced 6502". 2013-11-16. Retrieved 2016-04-02.
With the 65GZ032 Gideo Zweijtzer has built a VHDL core that is 6502 compatible, but extends the 8 bit core with a 32 bit design.
- "Measuring the ROR Bug in the Early MOS 6502". Retrieved 8 May 2011.
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- Matthews, Ian (June 4, 2007). "The Rise of MOS Technology & The 6502". Running Technologies Inc.
- MOS Technology 6500 Series Hardware Manual (PDF) (2nd ed.). Norristown, PA: MOS Technology. January 1976.
- MOS Technology 6500 Series Programming Manual (PDF) (2nd ed.). Norristown, PA: MOS Technology. January 1976.
- Zaks, Rodnay (1983). Programming the 6502 (4th ed.). Sybex. ISBN 0-89588-135-7.
- Zaks, Rodnay (1982). Advanced 6502 Programming. Sybex. ISBN 0-89588-089-X.
|Wikibooks has a book on the topic of: 6502 Assembly|
|Wikimedia Commons has media related to 6502 microprocessor.|
- 6502.org - the 6502 microprocessor resource – Repository and portal (Mike Naberezny)
- 650x information – Concise description, photos of MOS and second source chips; at cpu-collection.de (Dirk Oppelt)
- mdfs.net – 6502 instruction set
- Clever, Eric. "6502 - the first RISC µP". Archived from the original on 24 May 2012. – With link to concise 6502 programming chart in PDF
- Harrod, Dennette A. (October 1980). "6502 Gets Microprogrammable Instructions". BYTE. Vol. 5 no. 10. McGraw Hill. pp. 282–285. ISSN 0360-5280.
- U.S. Patent 3,991,307 Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results, which covers the 6502 decimal (BCD) mode
- Visual Transistor-level Simulation of the 6502 CPU
- List of 6502 software emulators – At Zophar's Domain (Sam Michaels)
- 6502 simulator for Windows – At Dan Boris' homepage hosted by The Atari Gaming Headquarters