Cadence Design Systems
Cadence Design Systems, Inc. is an American multinational electronic design automation (EDA) software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Cadence headquarters in San Jose, CA
|Industry||Software & Programming|
|Headquarters||San Jose, California, United States|
|Lip-Bu Tan, CEO|
|Revenue||2.146 billion USD (2018)|
|$351 million USD (2018)|
Number of employees
|7600 (Mar 30 2019)|
Cadence Design Systems, headquartered in San Jose, California, in the North San Jose Innovation District, is a supplier of electronic design technologies and engineering services in the electronic design automation (EDA) industry. The company develops software used to design chips and printed circuit boards, as well as intellectual properties (IP) covering a broad range of areas, including interfaces, memory, analog, SoC peripherals, data plane processing units, and verification.
Cadence products primarily target SoC design engineers and are used to move a design into packaged silicon, with products for custom and analog design, digital design, mixed-signal design, verification, and package/PCB design, as well as a broad selection of IP, and also hardware for emulation and FPGA prototyping.
To help integrate, verify, and implement complex digital SoCs, there are solutions that encompass design IP, timing analysis and signoff, services, and tools and methodologies. The company also provides products that assist with the development of complete hardware and software platforms that support end applications.
Cadence Design Systems was the result of a merger perfected in 1988 of Solomon Design Automation (SDA), co-founded in 1983 by Richard Newton, Alberto Sangiovanni-Vincentelli and James Solomon, and ECAD, co-founded by Glen Antle and Paul Huang in 1982. Joseph Costello was appointed as CEO from 1988–1997, and Cadence became the largest EDA company during his tenure.
Following Costello as CEO were Jack Harding (from 1997–99), Ray Bingham (from 1999-2005), and Mike Fister (from 2005-2008).
Following the resignation of Fister, the board appointed Lip-Bu Tan as acting CEO. In January 2009, the company confirmed Lip-Bu Tan as President and CEO. Tan had been most recently CEO of Walden International, a venture capital firm, and remains chairman of the firm. He has served on the Cadence Board of Directors since 2004, where he served on the Technology Committee for four years.
At the end of 2016, the company employed more than 7,100 people and reported 2016 revenues of approximately $1.82 billion. In November 2007 Cadence was named one of the "50 Best Places to Work in Silicon Valley" by San Jose Magazine.
Cadence's product offerings are targeted at various types of design and verification tasks which include:
- Custom IC technologies - Virtuoso Platform - Tools for designing full-custom integrated circuits; includes schematic entry, behavioral modeling (Verilog-AMS), circuit simulation, custom layout, physical verification, extraction and back-annotation. Used mainly for analog, mixed-signal, RF, and standard-cell designs, but also memory and FPGA designs.
- Digital & Signoff technologies - RTL to GDS II implementation: Genus Synthesis, Conformal Equivalence Checker, Stratus High Level Synthesis, Joules Power Analysis, Innovus Place & Route, Quantus RC Extraction, Tempus Timing Signoff, Voltus Power Integrity Signoff, Modus Automatic Test Pattern Generation.
- System & Verification technologies - Verification Suite - JasperGold Formal Verification, Xcelium simulation, Palladium Z1 emulation, Protium S1 FPGA prototyping, Perspec software-driven tests, vManager plan & metrics, Indago debug, and Verification IP catalog.
- Intellectual Property - Design IP targeting areas including memory / storage / high-performance interface protocols (USB or PCIe controllers and PHYs), Tensilica DSP processors for audio, vision, wireless modems and convolutional neural nets. Tensilica DSP processors IP include:
- PCB & Packaging technologies: Allegro Platform - Tools for co-design of integrated circuits, packages, and PCBs, including the Specctra auto-router. OrCAD/PSpice - Tools for smaller design teams and individual PCB designers., and Sigrity technologies - Tools for signal and power verification for system-level signoff verification and interface compliance.
In addition to EDA software, Cadence provides contracted methodology and design services as well as silicon design IP, and has a program aimed at making it easier for other EDA software to interoperate with the company's tools.
Cadence was involved in a 6-year-long legal dispute with Avanti Corporation, in which Cadence claimed Avanti stole Cadence code, and Avanti denied it. According to Business Week "The Avanti case is probably the most dramatic tale of white-collar crime in the history of Silicon Valley". The Avanti executives eventually pleaded no contest and Cadence received several hundred million dollars in restitution. Avanti was then purchased by Synopsys, which paid $265 million more to settle the remaining claims. The case resulted in a number of legal precedents.
The Cadence group Quickturn was also involved in a series of legal events with Mentor Graphics/Aptix. Mentor purchased rights to an Aptix patent, then sued Cadence. In this case, the CEO of Aptix, Amr Mohsen, forged a notebook in order to make the patent case stronger. When suspicions were raised, he staged a break-in of his own car to get rid of the evidence, resulting in charges of obstruction of justice. Trying to avoid this, he attempted to flee the country, only to be caught with an illegal passport and a pile of cash. While in jail for this offense, he was recorded offering money to intimidate witnesses and kill the judge. In order to fight the new charges, he tried to feign psychological problems, but left a trail of evidence of his research into this defense, and how it might be done. He was charged with attempting to delay a federal trial by feigning incompetency, but was convicted anyway. According to the lawyers concerned, the original notebooks were not needed for the trial. The patent filing date, which was not in dispute, would have sufficed.
- August 1993: acquired Comdisco Systems Inc, a provider of network design and optimization software.
- May 1997: acquired Cooper & Chyan Technology (CCT), a provider of PCB and IC automatic place and router software solutions (Specctra).
- December 1998: acquired Quickturn Design Systems, Inc., a market leader in microchip emulation.
- June 1999: acquired OrCAD Systems, a market leader in shrink-wrap PCB Design Tools.
- October 2002: acquired IBM's Test Design Automation group.
- January 2003: acquired Celestry Design Inc, a provider of fast-spice and reliability simulators.
- September 2003: acquired Verplex Systems, a provider of Formal Verification products, Conformal Solutions and Blacktie Property Checker.
- April 6, 2004: acquired Neolinear Technology, a privately held company specializing in rapid analog design technology.
- April 7, 2005: acquired Verisity, Ltd., a provider of verification process automation solutions ($315 million in cash).
- In 2007, the company began talks with Kohlberg Kravis Roberts and Blackstone Group regarding a possible sale of the company.
- July 12, 2007: acquired Invarium, a photolithography specialist.
- August 15, 2007: acquired Clearshape, a developer of Design for Manufacturability (DFM) technology.
- March 11, 2008: acquired ChipEstimate.com, an IP Portal and developer of IC planning and IP reuse management tools.
- August 15, 2008: Cadence withdrew a $1.6 billion offer to purchase rival Mentor Graphics.
- June 17, 2010: completed acquisition of Denali Software.
- May 10, 2011: acquired Altos Design Automation, Inc., vendor of standard and complex cell libraries for the delivery of complex SoCs at advanced nodes.
- July 12, 2011: acquired Azuro, creator of clock concurrent optimization technology.
- July 2, 2012: acquired Sigrity, a leader in high-speed PCB and IC packaging analysis
- February, 2013: acquired Cosmic Circuits, a provider of analog and mixed signal intellectual property (IP) cores. Cosmic Circuits offers IP products in connectivity and mixed-signal technologies in the 40 nm and 28 nm process nodes, with 20 nm and FinFET in development. The acquisition was completed in May 2013.
- March, 2013: acquired Tensilica, known for Dataplane Processing Units (DPU). Tensilica provides configurable and extensible processors along with DPUs for audio, baseband, imaging etc. It has 200 licensees and has shipped 2 billion cores so far.
- June, 2013: completed acquisition of the IP business of Evatronix, SA SKA of Poland. This acquisition brings to Cadence IP including certified USB 2.0/3.0, MIPI, display, and storage controllers.
- February 14, 2014: acquired Forte Design Systems, a provider of high-level synthesis (HLS) software products. This includes Cynthesizer, a SystemC-based behavioral synthesis tool that enables design creation at a higher level of abstraction.
- June 16, 2014: completed acquisition of Jasper Design Automation, Inc., a market and technology leader in the fast-growing formal analysis sector.
- April 28, 2016: completed acquisition of Rocketick Technologies, Ltd., an Israel-based pioneer and leading provider of multi-core parallel simulation.
The company has also acquired Valid Logic Systems, High Level Design (HLD), UniCAD, CadMOS, Ambit Design Systems, Simplex, Silicon Perspective, Plato and Get2Chip.
Denali Software, Inc. was an American software company, based in Sunnyvale, California, now acquired by Cadence. The company produces electronic design automation (EDA) software, intellectual property (IP) and design cores and platforms for memory, other standard interfaces and system-on-chip (SoC) design and verification. It has its engineering offices in Sunnyvale, Austin and Bangalore. Incorporated in 1996, Denali is headquartered in Sunnyvale, California and serves the global electronics industry with direct sales and support offices in North America, Europe, Japan and Asia.
On May 2010, Cadence Design Systems announced that it would acquire Denali for $315 million.
Valid Logic SystemsEdit
Valid Logic Systems was one of the first commercial electronic design automation (EDA) companies, now acquired by Cadence. It was founded in the early 1980s, along with Daisy Systems Corporation and Mentor Graphics, collectively known as DMV. The engineering founders were L. Curtis Widdoes, Tom McWilliams and Jeff Rubin, all of whom had worked on the S-1 supercomputer project at Livermore Labs.
Valid built both hardware and software, for schematic capture, logic simulation, static timing analysis, and packaging. Much of the initial software base derived from SCALD ("Structured Computer-Aided Logic Design"), a set of tools developed to support the design of the S-1 supercomputer at Lawrence Livermore National Laboratory. Later, Valid expanded into IC design tools and into printed circuit board layout.
At first, Valid ran schematic capture on a proprietary UNIX workstation, the SCALDSystem, with static timing analysis, simulation, and packaging running on a VAX or IBM-compatible mainframe. However, by the mid-1980s, general purpose workstations were powerful enough, and significantly cheaper. Companies such as Mentor Graphics and Cadence Design Systems sold software only for such workstations. By 1990, almost all Valid software was also running on workstations, primarily those from Sun Microsystems.
- Alberto Sangiovanni-Vincentelli, co-founder
- Richard Newton, co-founder
- James Solomon, co-founder
- Ken Keller, co-founder. Inventor of EDA framework including data store, portable window system, and layout editor
- Jiri Soukup, co-founder
- Ken Kundert, fellow. Creator of the Spectre circuit simulation family of products (including SpectreRF) and the Verilog-A analog hardware description language
- Joseph Costello, CEO, 1988–1997
- Lip-Bu Tan, CEO, 2009–present
- Anirudh Devgan, President, 2017-present
- Design on Diagonal Path in Pursuit of a Faster Chip, John Markoff, The New York Times, February 26, 2007
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- Former Azuro CEO Explains Clock Concurrent Optimization
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- Source: http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=061614_jasper
- Source: https://www.prnewswire.com/news-releases/cadence-completes-acquisition-of-rocketick-technologies-300259222.html
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- McWilliams, T.M.; Widdoes, L.C. Jr.; Wood, L.L. (1977-09-30). "Advanced digital processor technology base development for Navy applications: the S-1 project". Lawrence Livermore National Laboratory.
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