AMD RDNA Architecture
This article needs to be updated.September 2019)(
Radeon DNA (RDNA) is the codename for a GPU microarchitecture and accompanying instruction set developed by AMD for their GPUs as the successor to their GCN microarchitecture/instruction set. The first product lineup featuring RDNA will be the Radeon RX 5000 series of video card launched on July 7, 2019. The architecture is also planned to be used in mobile products and the upcoming next generation of game consoles by Sony and Microsoft.
It is likely to be RISC SIMD (or rather SIMT) microarchitecture. It is going to be manufactured and fabricated with TSMC's 7 nm FinFET graphics chips used in the Navi series of AMD Radeon graphics cards.
The architecture features a new processor design, although the first details released at AMD's Computex keynote hints at aspects from the previous a Graphics Core Next (GCN) architecture being present. It will feature multi-level cache hierarchy and an improved rendering pipeline, with support for GDDR6 memory. A completely redesigned (non-hybrid) architecture is planned as a successor (rumor).
Starting with the architecture itself, one of the biggest changes for RDNA is the width of a wavefront, the fundamental group of work. GCN in all of its iterations was 64 threads wide, meaning 64 threads were bundled together into a single wavefront for execution. RDNA drops this to a native 32 threads wide. At the same time, AMD has expanded the width of their SIMDs from 16 slots to 32 (aka SIMD32), meaning the size of a wavefront now matches the SIMD size.
RDNA also introduces working primitive shaders. While the feature was present in the hardware of the Vega architecture, it was difficult to get a real-world performance boost from and thus AMD never enabled it. Primitive shaders in RDNA are compiler-controlled.
GPUOpen hosts a pdf-document aiming to describe the environment, the organization and the program state of AMD “RDNA” Generation devices. It details the instruction set and the microcode formats native to this family of processors that are accessible to programmers and compilers.
The RDNA instruction set is owned by AMD (that also owns the X86-64 instruction set).
The RDNA instruction set is basically the GCN instruction set with several changes to.
Differences between RDNA and GCNEdit
There are architectural changes which affect how code is scheduled:
- Single cycle instruction issue:
- GCN issued one instruction per wave once every 4 cycles.
- RDNA issues instructions every cycle.
- GCN used a wavefront size of 64 threads (work items).
- RDNA supports both wavefront sizes of 32 and 64 threads.
- Workgroup Processors:
- GCN grouped the shader hardware into "compute units" (CUs) which contained scalar ALUs and vector ALUs, LDS and memory access. One CU contains 4 SIMD16s which share one path to memory.
- RDNA introduced the "workgroup processor" ("WGP"). The WGP replaces the compute unit as the basic unit of shader computation hardware/computing. One WGP encompasses 2 CUs. This allows significantly more compute power and memory bandwidth to be directed at a single workgroup. In RDNA 1 CU is one half of a WGP.
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