Instructions per cycle
This article needs additional citations for verification. (February 2008) (Learn how and when to remove this template message)
In computer architecture, instructions per cycle (IPC) is one aspect of a processor's performance: the average number of instructions executed for each clock cycle. It is the multiplicative inverse of cycles per instruction.
Calculation of IPCEdit
The calculation of IPC is done through running a set piece of code, calculating the number of machine-level instructions required to complete it, then using high-performance timers to calculate the number of clock cycles required to complete it on the actual hardware. The final result comes from dividing the number of instructions by the number of CPU clock cycles.
The number of instructions per second and floating point operations per second for a processor can be derived by multiplying the number of instructions per cycle with the clock rate (cycles per second given in Hertz) of the processor in question. The number of instructions per second is an approximate indicator of the likely performance of the processor.
The number of instructions executed per clock is not a constant for a given processor; it depends on how the particular software being run interacts with the processor, and indeed the entire machine, particularly the memory hierarchy. However, certain processor features tend to lead to designs that have higher-than-average IPC values; the presence of multiple arithmetic logic units (an ALU is a processor subsystem that can perform elementary arithmetic and logical operations), and short pipelines. When comparing different instruction sets, a simpler instruction set may lead to a higher IPC figure than an implementation of a more complex instruction set using the same chip technology; however, the more complex instruction set may be able to achieve more useful work with fewer instructions.
Factors governing IPCEdit
This section does not cite any sources. (July 2017) (Learn how and when to remove this template message)
A given level of instructions per second can be achieved with a high IPC and a low clock speed (like the AMD Athlon and early Intel's Core Series), or from a low IPC and high clock speed (like the Intel Pentium 4 and to a lesser extent the AMD Bulldozer). Both are valid processor designs, and the choice between the two is often dictated by history, engineering constraints, or marketing pressures.[original research?] However, a high IPC with a high frequency will always give the best performance.
Instructions per cycle for various processorsEdit
These numbers are not the IPC value of these CPUs but represent the theoretically possible Floating Point performance. Note that the numbers below only represent the logical widths of the processor's SIMD units. They do not account for the multiple SIMD pipes present in most architectures, nor do they represent the primary architectural definition of IPC, which measures the number of average scalar instructions retired per cycle, both integer, floating point, and control.
To get a theoretical GFLOPS (Billions of FLOPS) rating for a given CPU, multiply the number in this chart by the number of cores and then by the stock clock (in GHz) of a particular CPU model. For example, a Coffee Lake i7-8700K theoretically handles 32 Single-Precision floats per cycle, has 6 cores and a 3.7 GHz base clock. This gives it 32 x 6 x 3.7 = 710.4 GFLOPS.
It is important to note that Multithreading does NOT mean that two threads can operate on the same core simultaneously, sharing pipeline resources. Instead, the CPU allows one thread to use the core whilst another waits for data to arrive from memory, as in the case of a Cache miss. The operating system's scheduler can return the original thread to the queue, and then back into the CPU, once the data has been fetched. Thus, this feature does not have any effect on the theoretical floating point performance of a CPU, but, in certain cases, can help the CPU come closer to that performance, across multiple threads, in practice.
This section needs additional citations for verification. (July 2017) (Learn how and when to remove this template message)
|CPU Family||Dual precision DP IPC||Single precision SP IPC|
|Intel Core and Intel Nehalem (Harpertown?)||4||8|
|Intel Sandy Bridge and Intel Ivy Bridge||8||16|
|Intel Haswell - Intel Coffee Lake (and Devil's Canyon?)||16||32|
|Intel Ice Lake||?||?|
|Intel Xeon Skylake (AVX-512)||32||64|
|AMD Bulldozer, AMD Piledriver and AMD Steamroller
per module (two cores)
|AMD Ryzen and AMD Ryzen 2||16||32|
|AMD Ryzen 3 (7 nm)||?||?|
|Intel Atom (Bonnell, Saltwell, Silvermont and Goldmont)||2||4|
|AMD Jaguar and Puma||4||8|
|IBM PowerPC A2 (Blue Gene/Q), per core||8||SP elements are extend-|
ed to DP and processed
on the same units
|IBM PowerPC A2 (Blue Gene/Q), per thread||4|
|Intel Xeon Phi (Knights Corner), per core||16||32|
|Intel Xeon Phi (Knights Corner), per thread (4 per core)||8||16|
The useful work that can be done with any computer depends on many factors besides the processor speed. These factors include the instruction set architecture, the processor's microarchitecture, and the computer system organization (such as the design of the disk storage system and the capabilities and performance of other attached devices), the efficiency of the operating system, and most importantly the high-level design of the application software in use.
For users and purchasers of a computer system, instructions per clock is not a particularly useful indication of the performance of their system. For an accurate measure of performance relevant to them, application benchmarks are much more useful. Awareness of its existence is useful, in that it provides an easy-to-grasp example of why clock speed is not the only factor relevant to computer performance.