High Bandwidth Memory
High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stacked SDRAM from Samsung, AMD and SK Hynix. It is to be used in conjunction with high-performance graphics accelerators and network devices. The first HBM memory chip was produced by SK Hynix in 2013, and the first devices to use HBM were the AMD Fiji GPUs in 2015.
HBM achieves higher bandwidth while using less power in a substantially smaller form factor than DDR4 or GDDR5. This is achieved by stacking up to eight DRAM dies (thus being a Three-dimensional integrated circuit), including an optional base die with a memory controller, which are interconnected by through-silicon vias (TSVs) and microbumps. The HBM technology is similar in principle but incompatible with the Hybrid Memory Cube interface developed by Micron Technology.
HBM memory bus is very wide in comparison to other DRAM memories such as DDR4 or GDDR5. An HBM stack of four DRAM dies (4‑Hi) has two 128‑bit channels per die for a total of 8 channels and a width of 1024 bits in total. A graphics card/GPU with four 4‑Hi HBM stacks would therefore have a memory bus with a width of 4096 bits. In comparison, the bus width of GDDR memories is 32 bits, with 16 channels for a graphics card with a 512‑bit memory interface. HBM supports up to 4 GB per package.
The larger number of connections to the memory, relative to DDR4 or GDDR5, required a new method of connecting the HBM memory to the GPU (or other processor). AMD and Nvidia have both used purpose-built silicon chips, called interposers, to connect the memory and GPU. This interposer has the added advantage of requiring the memory and processor to be physically close, decreasing memory paths. However, as semiconductor device fabrication is significantly more expensive than printed circuit board manufacture, this adds cost to the final product.
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. The channels are completely independent of one another and are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses a 500 MHz differential clock CK_t / CK_c (where the suffix "_t" denotes the "true", or "positive", component of the differential pair, and "_c" stands for the "complementary" one). Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128‑bit data bus operating at double data rate (DDR). HBM supports transfer rates of 1 GT/s per pin (transferring 1 bit), yielding an overall package bandwidth of 128 GB/s.
The second generation of High Bandwidth Memory, HBM2, also specifies up to eight dies per stack and doubles pin transfer rates up to 2 GT/s. Retaining 1024‑bit wide access, HBM2 is able to reach 256 GB/s memory bandwidth per package. The HBM2 spec allows up to 8 GB per package. HBM2 is predicted to be especially useful for performance-sensitive consumer applications such as virtual reality.
In late 2018, JEDEC announced an update to the HBM2 specification, providing for increased bandwidth and capacities. Up to 307 GB/s per stack (2.4 Tbit/s effective data rate) is now supported in the official specification, though products operating at this speed had already been available. Additionally, the update added support for 12‑Hi stacks (12 dies) making capacities of up to 24 GB per stack possible.
A third generation of High Bandwidth Memory, HBM3, was announced by Samsung Electronics and SK Hynix at the 2016 Hot Chips conference. HBM3 is expected to offer increased memory capacity, greater bandwidth, lower voltage, and lower costs. The increased density is expected to come from greater density per die and more die stacks per chip. Bandwidth is expected to be 512 GB/s or greater. No release date has been announced, though Samsung expects volume production by 2020.
For the future of exascale high-performance computers, Hewlett Packard Enterprise predicts OPGHC HBM3+ and HBM4 to be released between 2022 and 2024. More stacking and higher capacity should bring more addressable memory per socket and higher speed. HBM3+ is planned with 4 TB/s and 1024 GB addressable memory per socket (for comparison, high-end AMD EPYC chips have 150 GB/s and 2048 GB addressable DDR4 DRAM per CPU socket). With 32 Gbit (4 GB) DRAM die and 16 dies per HBM3+ stack, each HBM3+ component would provide a capacity of 64 GB.
The commercial use of die-stacked memory was initially introduced in the flash memory industry. Toshiba introduced a NAND flash memory chip with eight stacked dies in April 2007, followed by Hynix Semiconductor introducing a NAND flash chip with 24 stacked dies in September 2007.
The development of High Bandwidth Memory began at AMD in 2008 to solve the problem of ever-increasing power usage and form factor of computer memory. Over the next several years, AMD developed procedures to solve die-stacking problems with a team led by Senior AMD Fellow Bryan Black. To help AMD realize their vision of HBM, they enlisted partners from the memory industry, particularly SK Hynix, which had prior experience with die-stacked memory, as well as partners from the interposer industry (UMC) and packaging industry (Amkor Technology and ASE).
The development of HBM was completed in 2013, when SK Hynix built the first HBM memory chip. HBM was adopted as industry standard JESD235 by JEDEC in October 2013, following a proposal by AMD and SK Hynix in 2010. High volume manufacturing began at a Hynix facility in Icheon, South Korea, in 2015.
In January 2016, Samsung Electronics began early mass production of HBM2. The same month, HBM2 was accepted by JEDEC as standard JESD235a. The first GPU chip utilizing HBM2 is the Nvidia Tesla P100 which was officially announced in April 2016.
At Hot Chips in August 2016, both Samsung and Hynix announced the next generation HBM memory technologies. Both companies announced high performance products expected to have increased density, increased bandwidth, and lower power. Samsung also announced a lower-cost version of HBM under development targeting mass markets. Removing the buffer die and decreasing the number of TSVs lowers cost, though at the expense of a decreased overall bandwidth (200 GB/s).
- ISSCC 2014 Trends Archived 2015-02-06 at the Wayback Machine page 118 "High-Bandwidth DRAM"
- "History: 2010s". SK Hynix. Retrieved 8 July 2019.
- Smith, Ryan (2 July 2015). "The AMD Radeon R9 Fury X Review". Anandtech. Retrieved 1 August 2016.
- Morgan, Timothy Prickett (March 25, 2014). "Future Nvidia 'Pascal' GPUs Pack 3D Memory, Homegrown Interconnect". EnterpriseTech. Retrieved 26 August 2014.
Nvidia will be adopting the High Bandwidth Memory (HBM) variant of stacked DRAM that was developed by AMD and Hynix
- High Bandwidth Memory (HBM) DRAM (JESD235), JEDEC, October 2013
- "JESD235a: High Bandwidth Memory 2". 2016-01-12.
- HBM: Memory Solution for Bandwidth-Hungry Processors Archived 2015-04-24 at the Wayback Machine, Joonyoung Kim and Younsu Kim, SK Hynix // Hot Chips 26, August 2014
- Where Are DRAM Interfaces Headed? // EETimes, 4/18/2014 "The Hybrid Memory Cube (HMC) and a competing technology called High-Bandwidth Memory (HBM) are aimed at computing and networking applications. These approaches stack multiple DRAM chips atop a logic chip."
- Highlights of the HighBandwidth Memory (HBM) Standard. Mike O’Connor, Sr. Research Scientist, NVidia // The Memory Forum – June 14, 2014
- Smith, Ryan (19 May 2015). "AMD Dives Deep On High Bandwidth Memory – What Will HBM Bring to AMD?". Anandtech. Retrieved 12 May 2017.
- "High-Bandwidth Memory (HBM)" (PDF). AMD. 2015-01-01. Retrieved 2016-08-10.
- Valich, Theo. "NVIDIA Unveils Pascal GPU: 16GB of memory, 1TB/s Bandwidth". VR World. Retrieved 2016-01-24.
- "Samsung Begins Mass Producing World's Fastest DRAM – Based on Newest High Bandwidth Memory (HBM) Interface". news.samsung.com.
- "Samsung announces mass production of next-generation HBM2 memory – ExtremeTech". 19 January 2016.
- Shilov, Anton (1 August 2016). "SK Hynix Adds HBM2 to Catalog". Anandtech. Retrieved 1 August 2016.
- "JEDEC Updates Groundbreaking High Bandwidth Memory (HBM) Standard" (Press release). JEDEC. 2018-12-17. Retrieved 2018-12-18.
- Walton, Mark (23 August 2016). "HBM3: Cheaper, up to 64GB on-package, and terabytes-per-second bandwidth". Ars Technica. Retrieved 3 February 2017.
- Ferriera, Bruno (23 August 2016). "HBM3 and GDDR6 emerge fresh from the oven of Hot Chips". Tech Report. Retrieved 3 February 2017.
- "TOSHIBA COMMERCIALIZES INDUSTRY'S HIGHEST CAPACITY EMBEDDED NAND FLASH MEMORY FOR MOBILE CONSUMER PRODUCTS". Toshiba. April 17, 2007. Retrieved 23 November 2010.
- "Hynix Surprises NAND Chip Industry". Korea Times. 5 September 2007. Retrieved 8 July 2019.
- High-Bandwidth Memory (HBM) from AMD: Making Beautiful Memory, AMD
- Smith, Ryan (19 May 2015). "AMD HBM Deep Dive". Anandtech. Retrieved 1 August 2016.
-  AMD Ushers in a New Era of PC Gaming including World’s First Graphics Family with Revolutionary HBM Technology
- Smith, Ryan (5 April 2016). "Nvidia announces Tesla P100 Accelerator". Anandtech. Retrieved 1 August 2016.
- "NVIDIA Tesla P100: The Most Advanced Data Center GPU Ever Built". www.nvidia.com.
- Smith, Ryan (23 August 2016). "Hot Chips 2016: Memory Vendors Discuss Ideas for Future Memory Tech – DDR5, Cheap HBM & More". Anandtech. Retrieved 23 August 2016.
- Walton, Mark (23 August 2016). "HBM3: Cheaper, up to 64GB on-package, and terabytes-per-second bandwidth". Ars Technica. Retrieved 23 August 2016.
- High Bandwidth Memory (HBM) DRAM (JESD235), JEDEC, October 2013
- Lee, Dong Uk; Kim, Kyung Whan; Kim, Kwan Weon; Kim, Hongjung; Kim, Ju Young; et al. (9–13 Feb 2014). "A 1.2V 8Gb 8‑channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV". 2014 IEEE International Solid-State Circuits Conference – Digest of Technical Papers. IEEE (published 6 March 2014): 432–433. doi:10.1109/ISSCC.2014.6757501. Retrieved 2019-04-13.
- HBM vs HBM2 vs GDDR5 vs GDDR5X Memory Comparison