Talk:CPUID
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Unnamed section #1 edit
CPUID is not specific to Intel Architecture, but its used in other CPUs as well, for example ARM MPCore [1], Altera NIOS2 [2]. In general, any architectural that supports Linux SMP kernel, must be able to uniquely identify underlaying processor to the kernel.
This page should be updated to incorporate this.
--Asadzia 07:56, 26 March 2007 (UTC)
IMO, the list of manufacturer IDs (specifically Transmeta) should be on individual lines, as the 2nd id for Transmeta was hiding. I'm gonna change it, unless theres a good reason why it was done this way. 79.79.213.203 (talk) 19:47, 17 November 2010 (UTC)
Unnamed section #2 edit
The first example code segfaults when I run it, compile with:
as -g cpuid.asm -o cpuid.o
ld -dynamic-linker /lib64/ld-linux-x86-64.so.2 -lc cpuid.o -o cpuid
Is this my error or is the source incorrect? My assembly isn't great, but shouldn't there be a
movl $1, %eax
int $0x80
Kobrien88 (talk) 03:16, 23 January 2011 (UTC)
- With the assemble/link commands you are using, yes, you are correct (at least on Linux.) I went ahead and changed the code. Should work with no segfaults now. Kabure (talk) 01:36, 14 February 2011 (UTC)
What is the rationale behind using assembly language snippets in this article? As shown under "..other languages" CPUID can be easily called from within C. As the majority of the assembly is about bit shifting, masking and formatting I'd consider C (or maybe even pseudo code) far more readable and giving more information to the average reader. I nobody speaks up, I'd like to replace the programs for the cache information and the brand string with C or pseudo code snippets. Also I'd like to add new leaves, especially AMD specific ones. To what detail shall this happen? Just a short description of the contained information or the full bit mask description? --APritzel (talk) 14:02, 1 August 2011 (UTC)
Hi, I get segfaults under Linux with Intel Compiler with the code in this article titled with "Or, a generally useful C implementation that works on 32 and 64 bit setups". The code was compiled als follows: icc -O0 -g test.c -o test. No segfault without -O0. Any idea? Disassembly:
Dump of assembler code for function cpuid:
0x000000000040056c <cpuid+0>: push %rbp
0x000000000040056d <cpuid+1>: mov %rsp,%rbp
0x0000000000400570 <cpuid+4>: sub $0x50,%rsp
0x0000000000400574 <cpuid+8>: mov %rbx,-0x18(%rbp)
0x0000000000400578 <cpuid+12>: mov %edi,-0x10(%rbp)
0x000000000040057b <cpuid+15>: mov %rsi,-0x50(%rbp)
0x000000000040057f <cpuid+19>: mov %rdx,-0x48(%rbp)
0x0000000000400583 <cpuid+23>: mov %rcx,-0x40(%rbp)
0x0000000000400587 <cpuid+27>: mov %r8,-0x38(%rbp)
0x000000000040058b <cpuid+31>: mov -0x50(%rbp),%rax
0x000000000040058f <cpuid+35>: mov -0x10(%rbp),%edx
0x0000000000400592 <cpuid+38>: mov %edx,(%rax)
0x0000000000400594 <cpuid+40>: mov -0x50(%rbp),%rax
0x0000000000400598 <cpuid+44>: mov -0x48(%rbp),%rdx
0x000000000040059c <cpuid+48>: mov -0x40(%rbp),%rcx
0x00000000004005a0 <cpuid+52>: mov -0x38(%rbp),%rbx
0x00000000004005a4 <cpuid+56>: mov %rax,-0x30(%rbp)
0x00000000004005a8 <cpuid+60>: mov (%rax),%eax
0x00000000004005aa <cpuid+62>: mov %rcx,-0x28(%rbp)
0x00000000004005ae <cpuid+66>: mov %rdx,-0x20(%rbp)
0x00000000004005b2 <cpuid+70>: mov %ebx,%edi
0x00000000004005b4 <cpuid+72>: cpuid
0x00000000004005b6 <cpuid+74>: mov %ebx,%esi
0x00000000004005b8 <cpuid+76>: mov %edi,%ebx
0x00000000004005ba <cpuid+78>: mov %edx,(%rbx)
0x00000000004005bc <cpuid+80>: mov -0x28(%rbp),%rdx
0x00000000004005c0 <cpuid+84>: mov %ecx,(%rdx)
0x00000000004005c2 <cpuid+86>: mov -0x20(%rbp),%rdx
0x00000000004005c6 <cpuid+90>: mov %esi,(%rdx)
0x00000000004005c8 <cpuid+92>: mov -0x30(%rbp),%rdx
0x00000000004005cc <cpuid+96>: mov %eax,(%rdx)
0x00000000004005ce <cpuid+98>: mov -0x18(%rbp),%rbx
0x00000000004005d2 <cpuid+102>: leaveq
0x00000000004005d3 <cpuid+103>: retq
End of assembler dump.
ECX is output-only? edit
There is nothing on the page (or to my knowledge anywhere else) which supports the assertion that the ECX register is ever involved in selecting a return value.
- the value in the EAX register, and in some cases the ECX register, specifies what information to return
Accordingly I propose that the highlit phrase be struck from the article. Martin Kealey (talk) 04:01, 21 August 2013 (UTC)
Extended function msb edit
The article says "To obtain extended function information CPUID should be called with the second most significant bit of EAX set. To determine the highest extended function calling parameter, call CPUID with EAX = 80000000h." Isn't 0x80000000 setting the most significant bit, rather than the 2nd msb? 110.77.158.29 (talk) 06:54, 24 February 2014 (UTC)
CPUID for input EAX=4 edit
Does useful stuff. Should be added. 188.27.81.64 (talk) 08:45, 10 July 2014 (UTC)
App note 485 gone edit
Even the removal notice thereof is gone from Intel's site, but the notice can still be read at http://web.archive.org/web/20130626034554/http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/processor-identification-cpuid-instruction-note.pdf 188.27.81.64 (talk) 09:58, 10 July 2014 (UTC)
External links modified edit
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KVM manufacturer ID string edit
The KVM manufacturer ID string is only 9 characters long - should it not be 12? — Preceding unsigned comment added by Joe Glancy (talk • contribs) 17:50, 10 June 2016 (UTC)
CPUID for input EAX=6 edit
EAX=06h CPUID
on return EAX:
Bit 00: Digital temperature sensor is supported if set.
Bit 01: Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLE[38]).
Bit 02: ARAT. APIC-Timer-always-running feature is supported if set.
Bit 03: Reserved.
Bit 04: PLN. Power limit notification controls are supported if set.
Bit 05: ECMD. Clock modulation duty cycle extension is supported if set.
Bit 06: PTM. Package thermal management is supported if set.
Bit 07: HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
Bit 08: HWP_Notification. IA32_HWP_INTERRUPT MSR is supported if set.
Bit 09: HWP_Activity_Window. IA32_HWP_REQUEST[bits 41:32] is supported if set.
Bit 10: HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.
Bit 11: HWP_Package_Level_Request. IA32_HWP_REQUEST_PKG MSR is supported if set.
Bit 12: Reserved.
Bit 13: HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are supported if set.
Bits 31 - 15: Reserved.
on return EBX:
Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor.
Bits 31 - 04: Reserved.
on return ECX:
Bit 00: Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF).
The capability to provide a measure of delivered processor performance (since last reset of the counters), as a percentage of the expected processor performance when running at the TSC frequency.
Bits 02 - 01: Reserved = 0.
Bit 03: The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).
Bits 31 - 04: Reserved = 0.
on return EDX:
Reserved = 0.
84.41.145.38 (talk) 16:20, 30 January 2018 (UTC)
Info from latest docs for cpuid 0x80000006 results showing 4 bit associativity code edit
@94.25.170.78: NOTE: ^6 is my shorthand for upper bit set in table below. Bit twiddling formula is my conversion from entry value to associativity value unoptimized. Associativity is now documented being in the top 4 bits of each 16 bit halfword in EAX and EBX, and the top 4 bits of the low halfword of ECX and EDX. A value of 6 means 8 way - see table below. Recently a value of 7 has been added to say use cpuid eax 4 ecx 2 results instead. See latest Intel ISA Prog Ref v42: [1] or [2]. Check cache info in /proc/cpuinfo if your system supports that, and/or install, or download and build, Todd Allen's cpuid package, and run the utility: it writes a paper about your cpu with one line per bit of info almost; Todd and I have exchanged info about AMD and Intel cpuid doc updates; and I track Linux-next cpuid and cpuinfo updates to keep Cygwin in sync, as well as being Cygwin cpuid package maintainer.
/* fn ^6 L2 cache and TLB */
/*
* L2/L3 4 bit associativity (1 << (a >> 1)) + (a & 1)*((1 << (a >> 1)) >> 1)
* 0 cache or TLB disabled 0 0 1 0 0 1 -> 0
* 1 direct mapped 1 0 1 0 0 1
* 2 2-way 10 1 10 0 1 10
* 4 4-way 100 10 100 0 10 100
* 6 8-way 110 11 1000 0 100 1000
* 7 use 0x00000004/2
* 8 16-way 1000 100 10000 0 1000 10000
* A 32-way 1010 101 100000 0 10000 100000
* B 48-way 1011 101 100000 1 10000 110000
* C 64-way 1100 110 1000000 0 100000 1000000
* D 96-way 1101 110 1000000 1 100000 1100000
* E 128-way 1110 111 10000000 0 1000000 10000000
* F fully associative 1111 111 10000000 1 1000000 11000000 -> 255
*/
/* Fn xfn Reg Off Len Name Description */
{ 0x80000006, 0, EAX, 0, 12, "l2itlb2ment" }, // l2 i TLB 2 MB page entries.
{ 0x80000006, 0, EAX, 12, 4, "l2itlb2massoc" }, // l2 i TLB 2 MB page assoc. See table.
{ 0x80000006, 0, EAX, 16, 12, "l2dtlb2ment" }, // l2 d TLB 2 MB page entries.
{ 0x80000006, 0, EAX, 28, 4, "l2dtlb2massoc" }, // l2 d TLB 2 MB page assoc. See table.
/* Fn xfn Reg Off Len Name Description */
{ 0x80000006, 0, EBX, 0, 12, "l2itlb4kent" }, // l2 i TLB 4 kB page entries.
{ 0x80000006, 0, EBX, 12, 4, "l2itlb4kassoc" }, // l2 i TLB 4 kB page assoc. See table.
{ 0x80000006, 0, EBX, 16, 12, "l2dtlb4kent" }, // l2 d TLB 4 kB page entries.
{ 0x80000006, 0, EBX, 28, 4, "l2dtlb4kassoc" }, // l2 d TLB 4 kB page assoc. See table.
/* Fn xfn Reg Off Len Name Description */
{ 0x80000006, 0, ECX, 0, 8, "l2chelnbytes" }, // l2 cache line size bytes.
{ 0x80000006, 0, ECX, 8, 4, "l2cheln/tag" }, // l2 cache lines/tag.
{ 0x80000006, 0, ECX, 12, 4, "l2cheassoc" }, // l2 cache assoc. See table.
{ 0x80000006, 0, ECX, 16, 16, "l2chekb" }, // l2 cache kB.
/* Fn xfn Reg Off Len Name Description */
{ 0x80000006, 0, EDX, 0, 8, "l3chelnbytes" }, // l3 cache line size bytes.
{ 0x80000006, 0, EDX, 8, 4, "l3cheln/tag" }, // l3 cache lines/tag.
{ 0x80000006, 0, EDX, 12, 4, "l3cheassoc" }, // l3 cache assoc. See table.
{ 0x80000006, 0, EDX, 16, 2, "[^6:d:16:17]" },
{ 0x80000006, 0, EDX, 18, 14, "l3chemb/2" }, // l3 cache 512kB.
24.64.172.44 (talk) 22:58, 8 January 2021 (UTC) Brian Inglis
does not include monitorx instructions edit
Ryzen cpus include the monitorx instruction set which should be listed under bit 29
from AMD official docs:
Support for the MONITORX instruction is indicated by CPUID Fn8000_0001_ECX[MONITORX] (bit 29) = 1.
source: https://www.amd.com/en/support/tech-docs?keyword=AMD64+Architecture+Programmer%27s+Manual%2C+Volumes+1-5 — Preceding unsigned comment added by Badasahog (talk • contribs) 15:35, 23 February 2022 (UTC)