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List of Intel CPU microarchitectures

x86 microarchitecturesEdit

Year Micro-architecture Pipeline stages Max
Clock

[MHz]

Tech
process

[nm]

1979 8086 (8086, 8088) 0 05 3000
1982 186 (80186, 80188) 0 025 3000
1982 286 (80286) 0 025 1500
1985 386 (80386) 03 033 1500
1989 486 (80486) 03 0100 1000
1993 P5 (Pentium) 05 0300 0600
1995 P6 (Pentium Pro;
later Pentium II)
14 (17 with load & store/retire) 0450 0350
1999 P6 (Pentium III)
(Copper Mine)
12 (15 with load & store/retire) 1400 0250
2000 NetBurst (Pentium 4)
(Willamette)
20 unified with branch prediction 2000 0180
2002 NetBurst (Pentium 4)
(Northwood, Gallatin)
3466 0130
2003 Pentium M 10 (12 with fetch/retire) 2133
2004 NetBurst (Pentium 4)
(Prescott)
31 unified with branch prediction 3800 0090
2006 Intel Core 12 (14 with fetch/retire) 3000 0065
2007 Penryn 3333 0045
2008 Nehalem 20 unified (14 without miss prediction) 3600
Bonnell 16 (20 with prediction miss) 2100
2010 Westmere 20 unified (14 without miss prediction) 3730 0032
2011 Saltwell 16 (20 with prediction miss) 2130
Sandy Bridge 14 (16 with fetch/retire) 4000
2012 Ivy Bridge 4100 0022
2013 Silvermont 14-17 (16-19 with fetch/retire) 2670
Haswell 14 (16 with fetch/retire) 4400
2014 Broadwell 3700 0014
2015 Airmont 14-17 (16-19 with fetch/retire) 2640
Skylake 14 (16 with fetch/retire) 4200
2016 Goldmont 20 unified with branch prediction 2600
Kaby Lake 14 (16 with fetch/retire) 4500
2017 Coffee Lake 5000
Goldmont Plus ? 20 unified with branch prediction ? 2800
2018 Cannon Lake 14 (16 with fetch/retire) 3200 0010
Whiskey Lake 4800 0014
Amber Lake 4200
2019 Cascade Lake 4400
Comet Lake 4900
Ice Lake 14-20 4100 0010
(2019) Cooper Lake 14 (16 with fetch/retire) 0014
(2019 /
2020)
Lakefield 14-20 0010
(2020) Tiger Lake 0010
(2021) Alder Lake 0010
(2022) Meteor Lake 0007
8086
first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. 8088 version, with an 8-bit bus, used in the original IBM Personal Computer.
186
included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus.
286
first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086. Included instructions relating to protected mode.
i386
first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
i486
Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
P5
original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction.
P6
used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC µop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".
NetBurst
Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.
Pentium M
updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
Intel Core
reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
  • Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.
Nehalem
released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
  • Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
Bonnell
45 nm, low-power, in-order microarchitecture for use in Atom processors.
  • Saltwell: 32 nm shrink of the Bonnell microarchitecture.
Larrabee (cancelled 2010)
multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).
Sandy Bridge
released January 9, 2011, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors, and in Pentium B9XX and Celeron B8XX series. Formerly called Gesher but renamed in 2007.[1] First x86 to introduce 256 bit AVX instruction set and implementation of YMM register.
  • Ivy Bridge: 22 nm shrink of the Sandy Bridge microarchitecture released April 28, 2012.
Silvermont
22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013.
  • Airmont: 14 nm shrink of the Silvermont microarchitecture.
Haswell
22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including FMA.
  • Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.
Skylake
14 nm microarchitecture, released August 5, 2015.
Goldmont
14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released April 2016.[3][4]
  • Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released December 11, 2017.
Ice Lake
a family of 10 nm microprocessors based on the new Sunny Cove microarchitecture, released in September, 2019.

Itanium microarchitecturesEdit

Merced
original Itanium microarchitecture. Used only in the first Itanium microprocessors.
McKinley
enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor.
Montecito
enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements.
Tukwila
enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, SMT, an integrated memory controller, QuickPath Interconnect, and other improvements.
Poulson
Itanium processor featuring a new microarchitecture.[5]
Kittson
the last Itanium microarchitecture. It has slightly higher clock speed than Poulson.

RoadmapEdit

Pentium 4 / Core LinesEdit

Pentium 4 / Core Roadmap
Fabrication
process
Micro-
architecture
Code
names
Core i
generation
Release
date
Processors
Desktop Mobile Enthusiast/WS 2P
Server/WS
4P/8P
Server
180 nm P6,
NetBurst
Willamette N/A 2000-11-20 Willamette Foster
130 nm Northwood/
Mobile Pentium 4
2002-01-07 Northwood Prestonia
Gallatin
090 nm Prescott 2004-02-01 Prescott Nocona
Irwindale
Paxville
065 nm Presler
Cedar Mill
Yonah
2006-01-05 Cedar Mill Yonah Presler Smithfield
Dempsey
Sossaman
Tulsa
Core Merom[6] 2006-07-27
[7][8]
Conroe Merom Kentsfield Woodcrest
Clovertown
Tigerton
045 nm Penryn 2007-11-11
[9]
Wolfdale Penryn Yorkfield Harpertown Dunnington
Nehalem Nehalem Previous[10] 2008-11-17
[11]
Lynnfield Clarksfield Bloomfield Gainestown Beckton
032 nm Westmere 2010-01-04
[12][13]
Clarkdale Arrandale Gulftown Westmere-EP Westmere-EX
Sandy
Bridge
Sandy Bridge 2 2011-01-09
[14]
Sandy Bridge Sandy Bridge-M Sandy Bridge-E Sandy Bridge-EP [15]
022 nm Ivy Bridge 3 2012-04-29 Ivy Bridge Ivy Bridge-M Ivy Bridge-E
[16]
Ivy Bridge-EP
[17]
Ivy Bridge-EX
[17]
Haswell Haswell 4 2013-06-02 Haswell-DT
[18]
Haswell-MB
(37–57W TDP, PGA package)
Haswell-H
(47W TDP, BGA package)
Haswell-ULP/ULX
(11.5–15W TDP)[18]
Haswell-E Haswell-EP Haswell-EX
Devil's
Canyon
2014-06 Haswell-DT N/A
014 nm Broadwell 5 2014-09-05 Broadwell-DT Broadwell-H (37–47W TDP)
Broadwell-U (15–28W TDP)
Broadwell-Y (4.5W TDP)
Broadwell-E Broadwell-EP
[19]
Broadwell-EX
[19]
Skylake Skylake 6 2015-08-05
[20]
Skylake-S Skylake-H (35–45W TDP)
Skylake-U (15–28W TDP)
Skylake-Y (4.5W TDP)
Skylake-X [21]
Skylake-W
Skylake-SP
(formerly Skylake-EP/-EX)[22]
Kaby Lake 7 / 8 2016-10 Kaby Lake-S Kaby Lake-G (65–100W TDP)
Kaby Lake-H (35–45W TDP)
Kaby Lake-U (15–28W TDP)
Kaby Lake-Y (4.5W TDP)
Kaby Lake-X
[21]
N/A
Coffee Lake 8 / 9 2017-10
[23]
Coffee Lake-S Coffee Lake-B (65W TDP)
Coffee Lake-H (35–45W TDP)
Coffee Lake-U (15–28W TDP)
N/A
Whiskey Lake 8 2018-08-28 N/A Whiskey Lake-U (15W TDP)
Amber Lake 8 / 10 Amber Lake-Y (5–7W TDP)
Skylake + DLBoost Cascade Lake N/A 2019-04-02 N/A Cascade Lake-X Cascade Lake-SP
Skylake Comet Lake 10 2019-09[a] Comet Lake-S Comet Lake-U (15W TDP)[24]
Comet Lake-Y (7W TDP)[24]
Skylake + DLBoost Cooper Lake 2019 / 2020 Cooper Lake-X Cooper Lake-SP
? Rocket Lake[25]
10 nm Skylake Cannon Lake 8 2018-05[a] N/A Cannon Lake-U (15W TDP) N/A
Sunny Cove[26] Ice Lake 10 2019-09[a] Ice Lake-U (15–28W TDP)[27]
Ice Lake-Y (9W TDP)[27]
Ice Lake-SP[28]
Willow Cove[29]? Tiger Lake[30] 2020[31]
? ? Sapphire Rapids 2021[32] Sapphire Rapids-SP
? Golden Cove[29] ? 2021[29]
007 nm[33] ? ? 2021[32]
005 nm[33]
Fabrication
process
Micro-
architecture
Code
names
Core i
generation
Release
date
Desktop Mobile Enthusiast/
WS
2P
Server/WS
4P/8P
Server
Processors
  1. ^ a b c retail availability

HybridEdit

Hybrid Roadmap
Fabrication
processes
Microarchitectures Code
names
Release
date
Processors/SoCs
Compute Die Base Die Package Core Atom MID, Smartphone Tablet Mobile Server
10 nm 14 nm 3D Foveros Sunny Cove Tremont Lakefield 2019 Lakefield N/A

Atom LinesEdit

Atom Roadmap[34]
Fabri-
cation
process
Micro-
archi-
tecture
Release
date
Processors/SoCs
MID, Smartphone Tablet Netbook Nettop Embedded Server Communication CE
45 nm Bonnell 2008 Silverthorne N/A Diamondville Tunnel Creek,
Stellarton
N/A Sodaville
2010 Lincroft Pineview Groveland
32 nm Saltwell 2011 Medfield (Penwell & Lexington),
Clover Trail+ (Cloverview)
Clover Trail (Cloverview) Cedar Trail (Cedarview) Unknown Centerton & Briarwood Unknown Berryville
22 nm Silvermont 2013 Merrifield (Tangier),[35] Slayton,
Moorefield (Anniedale)[36]
Bay Trail-T
(Valleyview)
Bay Trail-M
(Valleyview)
Bay Trail-D
(Valleyview)
Bay Trail-I
(Valleyview)
Avoton Rangeley Unknown
014 nm[34] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview) [37] Braswell [38] Denverton   Cancelled Unknown Unknown
Goldmont
[39]
2016 Broxton   Cancelled Willow Trail   Cancelled
Apollo Lake
Apollo Lake[40] Denverton [41] Unknown Unknown
Goldmont
Plus
[42]
2017 Unknown Unknown Gemini Lake[43] Unknown Unknown Unknown
10 nm Tremont 2019[29] Unknown Unknown Mercury Lake Unknown Unknown Unknown
Gracemont 2021[29]

See alsoEdit

ReferencesEdit

  1. ^ "An Update On Our Graphics-related Programs". May 25, 2010.
  2. ^ a b Cutress, Ian. "Spectre and Meltdown in Hardware: Intel Clarifies Whiskey Lake and Amber Lake". Retrieved 2018-09-02.
  3. ^ "Intel Software Development Emulator".
  4. ^ ""Goldmont"- the sequel to Silvermont Atom?".
  5. ^ Anton Shilov (June 19, 2007). "Intel Plans to change Itanium Micro-Architecture". X-bit Labs. Archived from the original on October 5, 2007. Retrieved 2007-10-05. Cite uses deprecated parameter |deadurl= (help)
  6. ^ Crothers, Brooke (2009-02-10). "Intel moves up rollout of new chips | Nanotech - The Circuits Blog - CNET News". News.cnet.com. Retrieved 2014-02-25.
  7. ^ "Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing".
  8. ^ "Intel Unveils World's Best Processor".
  9. ^ "Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology".
  10. ^ "ARK | Your source for information on Intel® products". Intel. 2013-05-30. Archived from the original on 2013-05-30. Retrieved 2013-05-30.
  11. ^ "Intel Launches Fastest Processor on the Planet". www.intel.com.
  12. ^ Mark Bohr (Intel Senior Fellow, Logic Technology Development) (2009-02-10). "Intel 32nm Technology" (PDF).
  13. ^ "Intel - Data Center Solutions, IoT, and PC Innovation". Intel.
  14. ^ "Intel Sandy Bridge chip coming January 5".
  15. ^ Pop, Sebastian. "Intel Ivy Bridge CPU Range Complete by Next Year".
  16. ^ "Ivy Bridge-E delayed until second half of 2013".
  17. ^ a b "Ivy Bridge EP and EX coming up in a year's time - the multi-socket platform heaven". 9 April 2012.
  18. ^ a b "Leaked specifications of Haswell GT1/GT2/GT3 IGP". Tech News Pedia. 2012-05-20. Retrieved 2014-02-25.
  19. ^ a b "Intel to release 22-core Xeon E5 v4 "Broadwell-EP" late in 2015 - KitGuru". www.kitguru.net.
  20. ^ "The wait for Skylake is almost over, first desktop chips likely to hit August 5". 6 July 2015.
  21. ^ a b Mujtaba, Hassan. "Intel X299 HEDT Platform For Skylake X and Kaby Lake X Processors Announcement on 30th May, Launch on 26th June – Reviews Go Live on 16th June". wccftech.com. Retrieved 2 May 2017.
  22. ^ Windeck, Christof. "Intel Xeon Gold, Platinum: Skylake-SP für Server "Mitte Sommer"". heise.de. Retrieved 2 May 2017.
  23. ^ "Coffee Lake: Intels 6C-Prozessoren erfordern neue Boards - Golem.de".
  24. ^ a b online, heise. "Comet Lake-U: 15-Watt-CPUs für Notebook-CPUs mit sechs Kernen". c't Magazin (in German). Retrieved 2019-08-21.
  25. ^ "Roadmap toont dat Intel in 2021 nog desktop-cpu's op 14nm maakt". Tweakers (in Dutch). Retrieved 2019-04-25.
  26. ^ Bright, Peter (2018-12-12). "Intel unveils a new architecture for 2019: Sunny Cove". Ars Technica. Retrieved 2018-12-12.
  27. ^ a b "Ice Lake Processor Family". Intel. Retrieved 2018-12-12.
  28. ^ "Server-CPUs: Cooper Lake und Ice Lake nutzen gleichen Sockel - Golem.de". www.golem.de (in German). Retrieved 2019-04-23.
  29. ^ a b c d e online, heise. "Intels neuer Anlauf mit "Sunny Cove", Gen-11-GPU und Chiplets". heise online (in German). Retrieved 2018-12-12.
  30. ^ "Intel's Cannonlake CPUs To Be Succeeded By 10nm Ice Lake Family in 2019 and 10nm Tiger Lake Family in 2019". WCCFTech. 2016-01-20.
  31. ^ Schilling, Andreas. "Neue Roadmaps von Intel bis 2023: GPUs ab 2021 in 7 nm". Hardwareluxx (in German). Retrieved 2019-05-10.
  32. ^ a b Shilov, Anton. "Intel Xeon Update: Ice Lake and Cooper Lake Sampling, Faster Future Updates". www.anandtech.com. Retrieved 2019-05-10.
  33. ^ a b "Intel currently developing 14nm, aiming towards 5nm chips - CPU - News". HEXUS.net. 2012-05-15. Retrieved 2014-02-25.
  34. ^ a b "Intel's Silvermont Architecture Revealed: Getting Serious About Mobile". AnandTech.
  35. ^ Hiroshige, Goto. "Intel Products for Tablets & SmartPhones" (PDF). 標準. Impress. Archived from the original (PDF) on 2013-11-14. Cite uses deprecated parameter |deadurl= (help)
  36. ^ "Import Data and Price of anniedale".
  37. ^ "アウトオブオーダーと最新プロセスを採用する今後のAtom".
  38. ^ "Products (Formerly Braswell)". Intel® ARK (Product Specs). Retrieved 5 April 2016.
  39. ^ Smith, Ryan; Cutress, Ian (29 April 2016). "Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Canceled". Anandtech.com. Retrieved 29 June 2016.
  40. ^ "Products (Formerly Apollo Lake)". Intel® ARK (Product Specs). Retrieved 6 January 2016.
  41. ^ "Products (Formerly Denverton)". Intel® ARK (Product Specs). Retrieved 6 January 2016.
  42. ^ https://www.anandtech.com/show/12146/intel-launches-gemini-lake-pentium-silver-and-celeron-socs-new-cpu-media-features
  43. ^ "Products (Formerly Gemini Lake)". Intel® ARK (Product Specs). Retrieved 11 December 2017.

External linksEdit