List of Intel CPU microarchitectures

The following is a partial list of Intel CPU microarchitectures. The list is incomplete. Additional details can be found in Intel's Tick-Tock model and Process-Architecture-Optimization model.

x86 microarchitecturesEdit

x86 microarchitectures
Year Micro-architecture Pipeline stages Max


Process node


1978 8086 (8086, 8088) 02 05 3000
1982 186 (80186, 80188) 02 025
1982 286 (80286) 03 025 1500
1985 386 (80386) 03 033
1989 486 (80486) 05 0100 1000
1993 P5 (Pentium) 05 0200 800, 600, 350
1995 P6 (Pentium Pro, Pentium II) 14 (17 with load & store/retire) 0450 500, 350, 250
1997 P5 (Pentium MMX) 06 0233 350
1999 P6 (Pentium III) 12 (15 with load & store/retire) 1400 250, 180, 130
2000 NetBurst (Pentium 4)
20 unified with branch prediction 2000 180
2002 NetBurst (Pentium 4)
(Northwood, Gallatin)
3466 130
2003 Pentium M (Banias, Dothan)
Enhanced Pentium M (Yonah)
10 (12 with fetch/retire) 2333 130, 90, 65
2004 NetBurst (Pentium 4, Pentium D)
31 unified with branch prediction 3800 90, 65
2006 Intel Core 12 (14 with fetch/retire) 3000 65
2007 Penryn (die shrink) 3333 45
2008 Nehalem 20 unified (14 without miss prediction) 3600
Bonnell 16 (20 with prediction miss) 2100
2010 Westmere (die shrink) 20 unified (14 without miss prediction) 3866 32
2011 Saltwell (die shrink) 16 (20 with prediction miss) 2130
Sandy Bridge 14 (16 with fetch/retire) 4000
2012 Ivy Bridge (die shrink) 4100 22
2013 Silvermont 14–17 (16–19 with fetch/retire) 2670
Haswell 14 (16 with fetch/retire) 4400
2014 Broadwell (die shrink) 3700 14
2015 Airmont (die shrink) 14–17 (16–19 with fetch/retire) 2640
Skylake 14 (16 with fetch/retire) 4200
2016 Goldmont 20 unified with branch prediction 2600
2017 Goldmont Plus ? 20 unified with branch prediction ? 2800
2018 Palm Cove 14 (16 with fetch/retire) 3200 10
2019 Sunny Cove 14–20 3900 10
2020 Tremont
Willow Cove 10
2021 Cypress Cove 14
Note: Atom microarchitectures are in Italic


first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. 8088 version, with an 8-bit bus, used in the original IBM Personal Computer.
included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus.
first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086. Included instructions relating to protected mode.

32-bit (IA-32)Edit

first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction.
used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".
commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.

64-bit (x86-64)Edit

reengineered P6-based microarchitecture used in Intel Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
  • Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.
released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
  • Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
Sandy Bridge
32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007.[1] First x86 to introduce 256 bit AVX instruction set and implementation of YMM register.
  • Ivy Bridge: successor to Sandy Bridge, using 22 nm process, released in April 2012.
22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including FMA.
  • Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.
14 nm microarchitecture, released August 5, 2015.
  • Kaby Lake: successor to Skylake, released in August 2016, broke Intel's Tick-Tock schedule due to delays with the 10 nm process.
    • Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes)[2]
    • Whiskey Lake: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities)[2]
  • Coffee Lake: successor to Kaby Lake, using 14+ nm process, released in October 2017
  • Cascade Lake: server and high-end desktop successor to Kaby Lake-X, using 14 nm process, released in April 2019
  • Comet Lake: successor to Coffee Lake, using 14++ nm process, released in August 2019[3]
  • Cooper Lake: server-only, optimized for AI oriented workloads using bfloat16, with limited availability only to Intel priority partners, using 14++ nm process, released in 2020[4][5]
Palm Cove
After releasing the Palm Cove core, Intel has changed their microarchitecture naming scheme, decoupling the CPU cores from their manufacturing nodes.[6][7]
Successor to Skylake (canceled), includes the AVX-512 instruction set.[8][9]
  • Cannon Lake: mobile-only successor of Kaby Lake, using Intel's 10 nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019.[10]
Sunny Cove
Successor to the Palm Cove core, first core to include hardware acceleration for SHA hashing algorithms.[11]
  • Ice Lake: low power, mobile-only successor to Whiskey Lake, using 10 nm process, released in September 2019
  • Ice Lake-SP: server-only successor to Cascade Lake, using 10 nm process, released in April 2021[4][12]
Cypress Cove
Backport of Sunny Cove to Intel's 14nm process
Willow Cove
Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem.[16]
  • Tiger Lake: successor to Ice Lake, using Intel's 10 nm SuperFin (10SF) process, released in Q4 2020
Golden Cove
Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions.[17]
  • Alder Lake: succeeds Rocket Lake and Tiger Lake; uses Intel's 10 nm Enhanced SuperFin (10ESF) process, to be released in 2021[18]
  • Sapphire Rapids: server-only, successor to Ice Lake-SP, using Intel's 10ESF process.[19]

x86 low-power (Atom)Edit

45 nm, low-power, in-order microarchitecture for use in Atom processors.
  • Saltwell: 32 nm shrink of the Bonnell microarchitecture.
22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013.
  • Airmont: 14 nm shrink of the Silvermont microarchitecture.
14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released April 2016.[20][21]
  • Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released December 11, 2017.
10 nm Atom microarchitecture iteration after Goldmont Plus.[22]
10 nm Atom microarchitecture iteration after Tremont. First Atom class core with AVX and AVX2 support.

Other microarchitecturesEdit

IA-64 (Itanium)Edit

original Itanium microarchitecture. Used only in the first Itanium microprocessors.
enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor.
enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements.
enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, SMT, an integrated memory controller, QuickPath Interconnect, and other improvements.
Itanium processor featuring a new microarchitecture.[23]
the last Itanium microarchitecture. It has slightly higher clock speed than Poulson.


a microarchitecture implementing the ARM architecture instruction set.
Larrabee (cancelled 2010)
multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).


Pentium 4 / Core linesEdit

Pentium 4 / Core roadmap
Core i
Desktop Mobile Enthusiast/WS 2P
180 nm P6,
Willamette N/A 2000-11-20 Willamette Foster
130 nm Northwood/
Mobile Pentium 4
2002-01-07 Northwood Northwood Mobile
Northwood-XE Prestonia
90 nm Prescott
2004-02-01 Prescott
Prescott 2M-XE
65 nm Cedar Mill
2006-01-05 Cedar Mill
Yonah Presler-XE Dempsey
Core Merom[24] 2006-07-27
Conroe Merom Kentsfield Woodcrest
45 nm Penryn 2007-11-11
Wolfdale Penryn Yorkfield Harpertown Dunnington
Nehalem Nehalem Previous[28] 2008-11-17
Lynnfield Clarksfield Bloomfield Gainestown Beckton
32 nm Westmere 2010-01-04
Clarkdale Arrandale Gulftown Westmere-EP Westmere-EX
Sandy Bridge 2 2011-01-09
Sandy Bridge Sandy Bridge-M Sandy Bridge-E Sandy Bridge-EP [33]
22 nm Ivy Bridge 3 2012-04-29 Ivy Bridge Ivy Bridge-M Ivy Bridge-E
Ivy Bridge-EP
Ivy Bridge-EX
Haswell Haswell 4 2013-06-02 Haswell-DT
(37–57W TDP, PGA package)
(47W TDP, BGA package)
(11.5–15W TDP)[36]
Haswell-E Haswell-EP Haswell-EX
2014-06 Haswell-DT N/A
14 nm Broadwell 5 2014-09-05 Broadwell-DT Broadwell-H (37–47W TDP)
Broadwell-U (15–28W TDP)
Broadwell-Y (4.5W TDP)
Broadwell-E Broadwell-EP
Skylake Skylake 6 2015-08-05
Skylake-S Skylake-H (35–45W TDP)
Skylake-U (15–28W TDP)
Skylake-Y (4.5W TDP)
(formerly Skylake-EP/-EX)[40]
Kaby Lake 7 / 8 2016-10 Kaby Lake-S Kaby Lake-G (65–100W TDP)
Kaby Lake-H (35–45W TDP)
Kaby Lake-U (15–28W TDP)
Kaby Lake-Y (4.5W TDP)
Kaby Lake-X
Coffee Lake 8 / 9 2017-10
Coffee Lake-S Coffee Lake-B (65W TDP)
Coffee Lake-H (35–45W TDP)
Coffee Lake-U (15–28W TDP)
Whiskey Lake 8 2018-08-28 N/A Whiskey Lake-U (15W TDP)
Amber Lake 8 / 10 Amber Lake-Y (5–7W TDP)
Skylake + DLBoost Cascade Lake N/A 2019-04-02 N/A Cascade Lake-X
Cascade Lake-W
Cascade Lake-SP
Cascade Lake-SP
Skylake Comet Lake 10 2019-09[a] Comet Lake-S Comet Lake-H (45W TDP)
Comet Lake-U (15W TDP)[42]
Comet Lake-Y (7W TDP)[42]
Skylake + DLBoost Cooper Lake N/A 2020-06 N/A[43][44] Cooper Lake-SP
Cypress Cove[45][46] Rocket Lake 11 2021-03 Rocket Lake-S N/A
10 nm Palm Cove Cannon Lake 8 2018-05[a] N/A Cannon Lake-U (15W TDP) N/A
Sunny Cove[47] Ice Lake 10 2019-09 (mobile)[a]
2021-04 (server)
N/A Ice Lake-U (15–28W TDP)[48]
Ice Lake-Y (9W TDP)[48]
N/A Ice Lake-SP[49] N/A
Willow Cove Tiger Lake 11 2020-09 N/A Tiger Lake-H (45 W)

Tiger Lake-H35 (28-35 W)

Tiger Lake-UP3 (12-28 W)
Tiger Lake-UP4 (7-15 W)

Golden Cove Alder Lake
12 2021[15][50] Alder Lake-S TBA Sapphire Rapids–SP[51]
Golden Cove Raptor Lake 13 2022 TBA Emerald Rapids–SP
7 nm TBA Meteor Lake 14 2023[52] TBA Granite Rapids–SP
TBA TBA Lunar Lake 15 2024 TBA
Codenames Core i
Desktop Mobile Enthusiast/
  1. ^ a b c retail availability


Hybrid roadmap
Microarchitectures Code
Compute die Base die Package Core Atom MID, smartphone Tablet Mobile Server
10 nm 14 nm 3D Foveros Sunny Cove Tremont Lakefield 2020 Lakefield N/A
Ryefield 2021/2022

Atom linesEdit

Atom roadmap[53]
MID, smartphone Tablet Netbook Nettop Embedded Server Communication CE
45 nm Bonnell 2008 Silverthorne N/A Diamondville Tunnel Creek,
N/A Sodaville
2010 Lincroft Pineview Groveland
32 nm Saltwell 2011 Medfield (Penwell & Lexington),
Clover Trail+ (Cloverview)
Clover Trail (Cloverview) Cedar Trail (Cedarview) Un­known Centerton & Briarwood Un­known Berryville
22 nm Silvermont 2013 Merrifield (Tangier),[54] Slayton,
Moorefield (Anniedale)[55]
Bay Trail-T
Bay Trail-M
Bay Trail-D
Bay Trail-I
Avoton Rangeley Un­known
014 nm[53] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview)[56] Braswell[57] Denverton   Cancelled Un­known Un­known
2016 Broxton   Cancelled Willow Trail   Cancelled
Apollo Lake
Apollo Lake[59] Denverton[60] Un­known Un­known
2017 Un­known Un­known Gemini Lake[62]
Gemini Lake Refresh[63]
Un­known Un­known Un­known
10 nm Tremont[22] 2020 Un­known Lakefield (hybrid) Lakefield (hybrid)
Elkhart Lake[64]
Jasper Lake [65]
Snow Ridge[66]
Un­known Un­known
Gracemont 2021[50] N/A Grand Ridge

See alsoEdit


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  4. ^ a b Cutress, Ian. "Intel's Cooper Lake Plans: The Chip That Wasn't Meant to Exist, Fades Away". AnandTech. Retrieved 2020-03-18.
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External linksEdit