This article needs attention from an expert on the subject. The specific problem is: Still an issue regarding 10nm/7nm terminology that isn't addressed in the 10 nanometer and 7 nanometer is a deviation from the International Technology Roadmap for Semiconductors definitions. In short, 7 nm Samsung/TSMC is equivalent to 10 nm Intel. Thus treating 10 nm Intel and 7 nm Samsung/TSMC at different articles due to marketing material not real measurements seems to be incorrect, specially when the pages refer to ITRS roadmap (duplicate note at other affected article. (April 2019)
In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.
All production "10 nm" processes are based on silicon CMOS finFET technology. Samsung first started their production of "10 nm" class chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by other products in 2016, and then for the Galaxy S8 in 2017. TSMC began commercial production of 10 nm chips in 2016, and Intel later began production of 10 nm chips in 2018.
The 10 nm process from Intel is similar to[ambiguous] the 7 nm processes offered by Samsung and TSMC, thus some argue that what really matters[neutrality is disputed] beyond 10 nm is transistor density (number of transistors per square milimeter).
In 2002, a team of researchers consisting of TSMC researcher Chenming Hu and UC Berkeley researchers including B. Yu, Leland Chang, Shibly Ahmed, Cyrus Tabery, Tsu-Jae King Liu and Jeffrey Bokor described a 10 nm FinFET process.
The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm.
In actuality, "10 nm" as it is generally understood in 2018 is only in high-volume production at Samsung. GlobalFoundries has skipped 10 nm, Intel has not yet started high-volume 10 nm production, due to yield issues, and TSMC has considered 10 nm to be a short-lived node, mainly dedicated to processors for Apple during 2017–2018, moving on to 7 nm in 2018.
There is also a distinction to be made between 10 nm as marketed by foundries and 10 nm as marketed by DRAM companies.
Technology production historyEdit
In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a 10 nm process. On 17 October 2016, Samsung Electronics announced mass production of SoC chips at 10 nm. The technology's main announced challenge has been triple patterning for its metal layer.
On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone which uses the company's version of the 10 nm processor. On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the 10 nm FinFET process.
On September 12, 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a 10 nm FinFET process and containing 4.3 billion transistors on a die of 87.66 mm2.
In April 2018, Intel announced a delay in volume production of 10 nm mainstream CPUs until sometime in 2019. In July the exact time was further pinned down to the holiday season. In the meantime, however, they did release a low-power 10 nm mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.
In June 2018 at VLSI 2018, Samsung announced their 11LPP and 8LPP processes. 11LPP is a hybrid based on Samsung 14nm and 10nm technology. 11LPP is based on their 10nm BEOL, not their 20nm BEOL like their 14LPP. 8LPP is based on their 10LPP process.
10 nm process nodesEdit
|ITRS Logic Device
|Process name||16/14 nm||11/10 nm||10 nm||11 nm||8nm||10 nm||10 nm[a]|
|Transistor density (MTr / mm²)||Unknown||Unknown||51.82||54.38||61.18||52.51||100.8[b]|
|Transistor Gate Pitch (nm)||70||48||68||?||64||66||54|
|Interconnect pitch (nm)||56||36||51||?||?||44||36|
|Transistor Fin Pitch (nm)||42||36||42||?||42||36||34|
|Transistor Fin Height (nm)||42||42||49||?||?||Unknown||53|
Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their 10 nm process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin height of Samsung's 10 nm process was updated by MSSCORPS CO at SEMICON Taiwan 2017.
For the DRAM industry, the "10 nm" node is often referred to as "10 nm-class" and this dimension generally refers to the half-pitch of the active area. The "10 nm" foundry structures are generally much larger. Samsung is also the most prominent player for 10 nm-class DRAM.[failed verification]
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- 10nm rollout
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- Samsung 10nm announcement
- triple patterning for 10nm metal
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Samsung 10LPE process
- "10 nm lithography process". wikichip.
- Samsung 10nm-class LPDDR4X
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