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In electronics, a multi-level cell (MLC) is a memory element capable of storing more than a single bit of information, compared to a single-level cell (SLC) which can store only one bit per memory element.

Triple-level cells (TLC) and quad-level cells (QLC) are versions of MLC memory, which can store 3 and 4 bits per cell, respectively. Note that due to the convention, the name "multi-level cell" is sometimes used specifically to refer to the "two-level cell", which is slightly confusing. Overall, the memories are named as follows:

  1. SLC (1 bit per cell) - fastest, highest cost
  2. eMLC (2 bits per cell) - faster than regular MLC
  3. MLC (2 bits per cell)
  4. TLC (3 bits per cell)
  5. QLC (4 bits per cell) - slowest, lowest cost

Examples of MLC memories are MLC NAND flash, MLC PCM (phase change memory), etc. For example, in SLC NAND flash technology, each cell can exist in one of the two states, storing one bit of information per cell. Most MLC NAND flash memory has four possible states per cell, so it can store two bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors. Multi-level cells which are designed for low error rates are sometimes called enterprise MLC (eMLC). There are tools for modeling the area/latency/energy of MLC memories.[1]

New technologies, such as multi-level cells and 3D Flash, and increased production volumes will continue to bring prices down.[2]


Single-level cellEdit

Flash memory stores data in individual memory cells, which are made of floating-gate transistors. Traditionally, each cell had two possible states, so one bit of data was stored in each cell in so-called single-level cells, or SLC flash memory. SLC memory has the advantage of faster write speeds, lower power consumption and higher cell endurance. However, because SLC memory stores less data per cell than MLC memory, it costs more per megabyte of storage to manufacture. Due to faster transfer speeds and expected longer life, SLC flash technology is used in high-performance memory cards. In February 2016, a study was published that showed little difference in practice between the reliability of SLC and MLC.[3]

A single-level cell (SLC) Flash memory may have a lifetime of about 50,000 to 100,000 program/erase cycles.[4][unreliable source?]

Multi-level cellEdit

The primary benefit of MLC flash memory is its lower cost per unit of storage due to the higher data density, and memory-reading software can compensate for a larger bit error rate.[5] The higher error rate necessitates an error correcting code (ECC) that can correct multiple bit errors; for example, the SandForce SF-2500 Flash Controller can correct up to 55 bits per 512-byte sector with an unrecoverable read error rate of less than one sector per 1017 bits read.[6] The most commonly used algorithm is Bose-Chaudhuri-Hocquenghem (BCH code).[7] Other drawbacks of MLC NAND are lower write speeds, lower number of program-erase cycles and higher power consumption compared to SLC flash memory.

Read speeds can also be lower for MLC NAND than SLC due to the need to read the same data at a second threshold voltage to help resolve errors. TLC and QLC devices may need to read the same data up to 4 and 8 times respectively to obtain values that are correctable by ECC.[8]

MLC flash may have a lifetime of about 1,000 to 10,000 program/erase cycles. This typically necessitates the use of a flash file system which is designed around the limitations of flash memory, such as using wear leveling to extend the useful lifetime of the flash device.

The Intel 8087 used two-bits-per-cell technology, and in 1980 was one of the first devices on the market to use multi-level ROM cells.[9][10] Some solid-state drives use part of an MLC NAND die as if it were single-bit SLC NAND, giving higher write speeds.[11][12][13]

Currently, all MLCs are planar-based (i.e. cells are built on silicon surface) and so subject to scaling limitations. To address this potential problem, the industry is already looking at technologies that can guarantee storage density increases beyond today’s limitations. One of the most promising is 3D Flash, where cells are stacked vertically, thereby avoiding the limitations of planar scaling. [14]

In the past, a few memory devices went the other direction and used two cells per bit to give even lower bit error rates.[15]

Triple-level cellEdit

Samsung announced a type of NAND flash that stores three bits of information per cell, with eight total voltage states. This is commonly referred to as Triple Level Cell (TLC) and was first seen in the 840 Series SSDs.[16] Samsung refers to this technology as 3-bit MLC. The negative aspects of MLC are amplified with TLC, but TLC benefits from still higher storage density and lower cost.[17]

Quad-level cellEdit

SanDisk X4 flash memory cards was one of the first products based on NAND-memory that stores four bits per cell, commonly referred to as Quad Level Cell (QLC), using 16 discrete charge levels (states) in each individual transistor.[18][19].

In 2018, ADATA, Intel, Micron, and Samsung have launched some SSD products using QLD NAND-memory[20][21][22][23].

See alsoEdit


  1. ^ "DESTINY: A Comprehensive Tool with 3D and Multi-level Cell Memory Modeling Capability", Mittal et al., JLPEA, 2017
  2. ^,12728.html, NAND Flash is displacing Hard Disk Drives, Retrieved 29. May 2018
  3. ^ Bianca Schroeder and Arif Merchant (February 22, 2016). "Flash Reliability in Production: The Expected and the Unexpected". Conference on File and Storage Technologies. Usenix. Retrieved November 3, 2016.
  4. ^,12728.html, NAND Flash is displacing Hard Disk Drives, Retrieved 29. May 2018
  5. ^ Micron's MLC NAND Flash Webinar Archived 2007-07-22 at the Wayback Machine
  6. ^ SandForce SF-2600/SF-2500 Product Info 2013-10-22
  7. ^ A Tour of the Basics of Embedded NAND Flash Options EE Times 2013-08-27
  8. ^ Peleato; et al. (Sep 2015). "Adaptive Read Thresholds for NAND Flash". IEEE Transactions on Communications. 63 (9): 3069–3081. doi:10.1109/TCOMM.2015.2453413. Retrieved 22 October 2018.
  9. ^ "Four-state cell called density key" article by J. Robert Lineback. "Electronics" magazine. 1982 June 30.
  10. ^ P. Glenn Gulak. "A Review of Multiple-Valued Memory Technology"
  11. ^ Geoff Gasior. "Samsung's 840 EVO solid-state drive reviewed: TLC NAND with a shot of SLC cache". 2013.
  12. ^ Allyn Malventano. "New Samsung 840 EVO employs TLC and pseudo-SLC TurboWrite cache". 2013.
  13. ^ Samsung. "Samsung Solid State Drive: TurboWrite Technology White Paper". 2013.
  14. ^,12728.html - Solid State bit Density and the Flash Memory Controller, Retrieved 29. May 2018
  15. ^ "Automotive EEPROMs use two cells per bit for ruggedness, reliability" by Graham Prophet 2008-10-02
  16. ^ Samsung SSD 840 Series - 3BIT/MLC NAND Flash
  17. ^ "Samsung SSD 840: Testing the Endurance of TLC NAND". AnandTech. 2012-11-16. Retrieved 2014-04-05.
  18. ^ SanDisk Ships World’s First Flash Memory Cards with 64 Gigabit X4 (4-Bits-Per-Cell) NAND Flash Technology
  19. ^ NAND Flash - The New Era of 4 bit per cell and Beyond EE Times 2009-05-05
  20. ^ Shilov, Anton. "ADATA Reveals Ultimate SU630 SSD: 3D QLC for SATA". Retrieved 2019-05-13.
  21. ^ Tallis, Billy. "The Intel SSD 660p SSD Review: QLC NAND Arrives For Consumer SSDs". Retrieved 2019-05-13.
  22. ^ Tallis, Billy. "The Crucial P1 1TB SSD Review: The Other Consumer QLC SSD". Retrieved 2019-05-13.
  23. ^ Shilov, Anton. "Samsung Starts Mass Production of QLC V-NAND-Based SSDs". Retrieved 2019-05-13.

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