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The ETRAX CRIS is a series of CPUs designed and manufactured by Axis Communications for use in embedded systems since 1993. The name is an acronym of the chip's features: Ethernet, Token Ring, AXis - Code Reduced Instruction Set. Token ring support has been taken out from the latest chips as it has become obsolete.
Types of chipsEdit
The TGA (Twinax Gate Array), developed in 1986, was a communications transceiver for the AS/400 architecture.
The First chip with embedded microcontroller was the CGA-1 (Coax Gate Array) which contained both IBM 3270 (coax) communications and AS/400 communications (Twinax). It also had a small microcontroller and various IO:s, including serial and parallel interfaces. The 1 chip was designed by Martin Gren, the bug-fixed CGA-2 by Martin Gren and Staffan Göransson.
In 1993, by introducing 10 Mbit/s Ethernet and Token Ring controllers, the name ETRAX was born.
The ETRAX-4 had improved performance over previous models and an SCSI controller.
In 2000, the ETRAX 100LX design added an MMU, as well as USB, synchronous serial and SDRAM support. Its CPU performance was raised to 100 MIPS. Since it has an MMU, it could run the Linux kernel without modifications (low-level support for the ETRAX CPU had to be added). As of Linux kernel 4.17 the architecture has been dropped due to being obsolete.
- A 32-bit RISC CPU core
- 10/100 Mbit/s Ethernet controller
- 4 asynchronous serial ports
- 2 synchronous serial ports
- 2 USB ports
- 2 Parallel ports
- 4 ATA (IDE) ports
- 2 Narrow SCSI ports (or 1 Wide)
- Support for SDRAM, Flash, EEPROM, SRAM
The device comes in a 256-pin Plastic Ball Grid Array (PBGA) package and uses 350 mW power (typical).
ETRAX 100LX MCMEdit
This system-on-a-chip is an ETRAX 100LX plus flash memory, SDRAM, and an Ethernet PHYceiver. There were two versions commercialized: the ETRAX 100LX MCM 2+8 (2 MB flash, 8 MB SDRAM), and the ETRAX MCM 4-16 (4 MB flash, 16 MB SDRAM).
Designed in 2005, and with full Linux 2.6 support, this chip features:
- A 200 MIPS, 32-bit RISC with 5 stage pipeline CRIS CPU core with 16 kB data and 16 kB instruction cache and a MMU.
- Two 10/100 Mbit/s Ethernet controllers
- Crypto accelerator, supporting AES, DES, Triple DES, SHA-1 and MD5.
- 128 kB on-chip RAM
- A microprogrammable I/O processor, supporting PC-Card, CardBus, PCI, USB FS/HS host, USB FS device, SCSI and ATA.
The device comes in a 256-pin Plastic Ball Grid Array package and uses 465 mW power (typical).
- Axis Communications AXIS 82 developer board
- Embedded Linux PC from ipcas
- ACME Systems' FOX board
- Elphel Reconfigurable Network Camera based on Etrax FS and Xilinx Spartan 3e FPGA
- Free2move's embedded Linux system
- Rcotel Corporation's single board Linux computer
- DSP&FPGA's industrial control unit
- BBDevice.com remote control systems
Operating system supportEdit
This section needs expansion. You can help by adding to it. (April 2018)
In April 2018 it was announced that Linux would stop supporting this architecture.
- axis.com - Axis Chip Development History Archived May 30, 2010, at the Wayback Machine.
- "30 years of milestones" (PDF). Axis Communications.
- The linux kernel source-code under /arch/chris contained the low-level CPU-specific additions required to make the Linux kernel able to run on the ETRAX/Cris CPUs. (See for example https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/cris?h=v4.13-rc4)
- "Showroom @". Developer.axis.com. Retrieved 2009-04-09.
- Arnd Bergmann (April 2, 2018). "[GIT PULL] arch: remove obsolete architecture ports". linux-kernel (Mailing list).