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The ARM Cortex-A53 is one of the first two microarchitectures implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A53 is a 2-wide decode superscalar processor, capable of dual-issuing some instructions. It was announced October 30th, 2012 and is marketed by ARM as either a stand-alone, more energy-efficient alternative to the more powerful Cortex-A57 microarchitecture, or to be used alongside a more powerful microarchitecture in a big.LITTLE configuration. It is available as an IP core to licensees, like other ARM intellectual property and processor designs.
|Designed by||ARM Holdings|
|L1 cache||8–64 KiB|
|L2 cache||128 KiB – 2 MiB|
|Architecture and classification|
|Products, models, variants|
|Product code name(s)|
- 8-stage pipelined processor with 2-way superscalar, in-order execution pipeline
- DSP and NEON SIMD extensions are mandatory per core
- VFPv4 Floating Point Unit onboard (per core)
- Hardware virtualization support
- TrustZone security extensions
- 64-byte cache lines
- 10-entry L1 TLB, and 512-entry L2 TLB
- 4 KiB conditional branch predictor, 256-entry indirect branch predictor
The Cortex-A53 is the most widely used architecture for mobile SoCs since 2014 to the present day, making it one of the longest-running ARM processors for mobile devices. It is currently featured in most entry-level and lower mid-range SoCs, while higher-end SoCs used the newer ARM Cortex-A55.
The processor is used in the ODROID-C2 and in Roku streaming media players (in the high-end models from 2016 and in all models released between 2017-2018). Another notable Cortex-A53 application is the Pine A64/A64+ single-board computer.
These cores are used in a 24-core SoC, the Socionext SynQuacer SC2A11.
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