The K5 is AMD's first x86 processor to be developed entirely in-house. Introduced in March 1996, its primary competition was Intel's Pentium microprocessor. The K5 was an ambitious design, closer to a Pentium Pro than a Pentium regarding technical solutions and internal architecture. However, the final product was closer to the Pentium regarding performance, although faster clock-for-clock compared to the Pentium.
An AMD K5 PR166 microprocessor
|Launched||March 27, 1996 (SSA/5)|
October 7, 1996 (5k86)
|Max. CPU clock rate||75 MHz to 133 MHz|
|FSB speeds||50 MHz to 66 MHz|
|L1 cache||8 KB + 16 KB|
(data + instructions)
|Architecture and classification|
|Products, models, variants|
The K5 was based upon an internal highly parallel 29k RISC processor architecture with an x86 decoding front-end. The K5 offered good x86 compatibility and the in-house-developed test suite proved invaluable on later projects. All models had 4.3 million transistors, with five integer units that could process instructions out of order and one floating-point unit. The branch target buffer was four times the size of the Pentium's and register renaming helped overcome register dependencies. The chip's speculative execution of instructions reduced pipeline stalls. It had a 16 KB four-way set-associative instruction cache and an 8 KB data cache. The floating-point divide and square-root microcode were mechanically proven. The floating-point transcendental instructions were implemented in hardware and were faithful to true mathematical results for all operands.
The K5 project represented an early chance for AMD to take technical leadership from Intel. Although the chip addressed the right design concepts, the actual engineering implementation had its issues. The low clock rates were, in part, due to AMD's limitations as a "cutting edge" manufacturing company at the time, and in part due to the design itself, which had many levels of logic for the process technology of the day, hampering clock scaling. Additionally, while the K5's floating-point performance was regarded as superior to that of the Cyrix 6x86[clarification needed], it was slower than that of the Pentium, although while offering more reliable transcendental function results. Because it was late to market and did not meet performance expectations, the K5 never gained the acceptance among large computer manufacturers that the Am486 and AMD K6 enjoyed.
There were two revisions of the K5 architecture, internally called the SSA/5 and the 5k86, both released with the K5 label. The original set of "SSA/5" CPUs had its branch prediction unit disabled and additional internal waitstates added; these issues were remedied with the "5k86", resulting in up to 30% better performance clock for clock. The "SSA/5" line ran from 75 to 100 MHz; the "5k86" line ran from 90 to 133 MHz. However, AMD used what it called a PR rating, or performance rating, to label the chips according to their suggested equivalence in integer performance to a Pentium of that clock speed. Thus, a 116 MHz chip from the second line was marketed as the "K5 PR166". Manufacturing delays caused the PR200's arrival to nearly align with the release of K6. Since AMD did not want the two chips competing, the K5-PR200 only arrived in small numbers.
- Sold as 5K86 P75 to P100, later as K5 PR75 to PR100
- 4.3 million transistors in 500 or 350 nm
- L1-Cache: 8 + 16 KB (data + instructions)
- Socket 5 and Socket 7
- VCore: 3.52 V
- Front side bus: 50 (PR75), 60 (PR90), 66 MHz (PR100)
- First release: March 27, 1996
- Clockrate: 75, 90, 100 MHz
- J. Strother Moore, Thomas W. Lynch, Matt Kaufmann, "A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program", IEEE Transactions on Computers, Volume 47 Issue 9, September 1998. Pages 913–926. IEEE Computer Society Washington, DC, USA.
- David M. Russinoff, "A Mechanically Checked Proof of Correctness of the AMD K5 Floating Point Square Root Microcode", Formal Methods in System Design archive, Volume 14 Issue 1, January 1999. Pages 75–125. Kluwer Academic Publishers Hingham, MA, USA.
- T. Lynch, A. Ahmed, M. Schulte, T. Callaway, R. Tisdale "K5 Transcendental Functions", Proceedings of the 12th Symposium on Computer Arithmetic. 19–21 July 1995. Pages 163–170. IEEE Computer Society Washington, DC, USA.