PWRficient processors comply with the 64-bit Power ISA, and are designed for high performance and extreme power efficiency. The processors are highly modular and can be combined to multi-core system-on-a-chip designs, combining CPU, northbridge, and southbridge functionality on a single processor die.
The PA6T was the first and only processor core from P.A. Semi, and it was offered in two distinct lines of products, 16xxM dual core processors and 13xxM/E single core processors. The PA6T lines differed in their L2 cache size, their memory controllers, their communication functionality, and their cryptography offloading features. At one time, P.A. Semi had plans to offer parts with up to 16 cores.
The PA6T core is the first Power ISA core to be designed from scratch outside the AIM alliance (i.e. not designed by IBM, Motorola/Freescale, or Apple Inc.) in ten years. Since Texas Instruments was one of the investors in P.A. Semi, it was suggested that their fabrication plants would have been used to manufacture the PWRficient processors.
PWRficient processors were initially shipped to select customers in February 2007 and were released for worldwide sale in Q4 2007.
P.A. Semi was bought by Apple Inc. in April 2008, and closed down development of PWRficient architecture processors. However, it will continue to manufacture, sell and support these components for the foreseeable future due to an agreement with the US Government, as the processors are used in some military applications.
|Designed by||P.A. Semi|
|Max. CPU clock rate||1.8 GHz to 2.0 GHz|
|L1 cache||64+64 KB/core|
|L2 cache||2 MB/core|
|Architecture and classification|
|Min. feature size||65 nm|
|Instruction set||Power ISA (Power ISA v.2.04)|
PWRficient processors comprise three parts:
- Superscalar, out-of-order 32-bit/64-bit Power ISA processor core
- Adheres to the Power ISA v.2.04
- Little endian or big endian operation
- 64/64 kB instruction and data L1 caches. 32 GB/s bandwidth.
- Six execution units including a double precision FPU and Altivec unit
- Hypervisor and virtualization support
- Maximum 7 W at 2 GHz
- 11 million transistors, 10 mm² large @ 65 nm.
- scalable cross-bar interconnect
- 1–8 SMP cores
- 1–2 L2 caches, 512 KB – 8 MB large. 16 GB/s bandwidth.
- 1–4 1067 MHz DDR2 memory controllers. 16 GB/s bandwidth.
- 64 GB/s peak bandwidth
- MOESI coherency
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- PA Semi attacks performance/Watt
- FPF 2005: P.A. Semi's PA6T-1682M System on a Chip – Real World Technologies
- Judicious Clocking Subdues Power-Architecture Cooling Needs – Electronic Design