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RTL8201 Ethernet PHY chip

PHY is an abbreviation for the physical layer of the OSI model and refers to the circuitry required to implement physical layer functions.

A PHY connects a link layer device (often called MAC as an acronym for medium access control) to a physical medium such as an optical fiber or copper cable. A PHY device typically includes both Physical Coding Sublayer (PCS) and Physical Medium Dependent (PMD) layer functionality.[1]

Example usesEdit

Ethernet physical transceiverEdit

Micrel KS8721CL - 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver

The Ethernet PHY is a component that operates at the physical layer of the OSI network model. It implements the Ethernet physical layer portion of the 1000BASE-T, 100BASE-TX, and 10BASE-T standards.

More specifically, the Ethernet PHY is a chip that implements the hardware send and receive function of Ethernet frames; it interfaces between the analog domain of Ethernet's line modulation and the digital domain of link-layer packet signaling.[2] The PHY usually does not handle MAC addressing, as that is the link layer's job. Similarly, Wake-on-LAN and Boot ROM functionality is implemented in the network interface card (NIC), which may have PHY, MAC, and other functionality integrated into one chip or as separate chips.

Examples include the Microsemi SimpliPHY and SynchroPHY VSC82xx/84xx/85xx/86xx family, Marvell Alaska 88E1310/88E1310S/88E1318/88E1318S Gigabit Ethernet transceivers and offerings from Intel[3] and ICS.[4]


  1. ^ Mauricio Arregoces; Maurizio Portolani. "Data Center Fundamentals". Retrieved 2015-11-18.
  2. ^ "microcontroller - what is the difference between PHY and MAC chip - Electrical Engineering Stack Exchange". 2013-07-11. Retrieved 2015-11-18.
  3. ^ Intel PHY controllers brochure
  4. ^ - ICS1890 10Base-T/100Base-TX Integrated PHYceiver datasheet