The Manchester computers were an innovative series of stored-program electronic computers developed during the 30-year period between 1947 and 1977 by a small team at the University of Manchester, under the leadership of Tom Kilburn. They included the world's first stored-program computer, the world's first transistorised computer, and what was the world's fastest computer at the time of its inauguration in 1962.
The project began with two aims: to prove the practicality of the Williams tube, an early form of computer memory based on standard cathode ray tubes (CRTs); and to construct a machine that could be used to investigate how computers might be able to assist in the solution of mathematical problems. The first of the series, the Manchester Baby, ran its first program on 21 June 1948. As the world's first stored-program computer, the Baby, and the Manchester Mark 1 developed from it, quickly attracted the attention of the United Kingdom government, who contracted the electrical engineering firm of Ferranti to produce a commercial version. The resulting machine, the Ferranti Mark 1, was the world's first commercially available general-purpose computer.
The collaboration with Ferranti eventually led to an industrial partnership with the computer company ICL, who made use of many of the ideas developed at the university, particularly in the design of their 2900 series of computers during the 1970s.
The Manchester Baby was designed as a test-bed for the Williams tube, an early form of computer memory, rather than as a practical computer. Work on the machine began in 1947, and on 21 June 1948 the computer successfully ran its first program, consisting of 17 instructions written to find the highest proper factor of 218 (262,144) by trying every integer from 218 − 1 downwards. The program ran for 52 minutes before producing the correct answer of 131,072.
The Baby was 17 feet (5.2 m) in length, 7 feet 4 inches (2.24 m) tall, and weighed almost 1 long ton. It contained 550 thermionic valves – 300 diodes and 250 pentodes – and had a power consumption of 3.5 kilowatts. Its successful operation was reported in a letter to the journal Nature published in September 1948, establishing it as the world's first stored-program computer. It quickly evolved into a more practical machine, the Manchester Mark 1.
Manchester Mark 1Edit
Development of the Manchester Mark 1 began in August 1948, with the initial aim of providing the university with a more realistic computing facility. In October 1948 UK Government Chief Scientist Ben Lockspeiser was given a demonstration of the prototype, and was so impressed that he immediately initiated a government contract with the local firm of Ferranti to make a commercial version of the machine, the Ferranti Mark 1.
Two versions of the Manchester Mark 1 were produced, the first of which, the Intermediary Version, was operational by April 1949. The Final Specification machine, which was fully working by October 1949, contained 4,050 valves and had a power consumption of 25 kilowatts. Perhaps the Manchester Mark 1's most significant innovation was its incorporation of index registers, commonplace on modern computers.
Meg and MercuryEdit
As a result of experience gained from the Mark 1, the developers concluded that computers would be used more in scientific roles than pure maths. They therefore embarked on the design of a new machine which would include a floating point unit; work began in 1951. The resulting machine, which ran its first program in May 1954, was known as Meg, or the megacycle machine. It was smaller and simpler than the Mark 1, as well as quicker at solving maths problems. Ferranti produced a commercial version marketed as the Ferranti Mercury, in which the Williams tubes were replaced by the more reliable core memory.
Work on building a smaller and cheaper computer began in 1952, in parallel with Meg's ongoing development. Two of Kilburn's team, Richard Grimsdale and D. C. Webb, were assigned to the task of designing and building a machine using the newly developed transistors instead of valves. Initially the only devices available were germanium point-contact transistors, less reliable than the valves they replaced but which consumed far less power.
Two versions of the machine were produced. The first was the world's first transistorised computer, and became operational in November 1953. The second version was completed in April 1955. The 1955 version used 200 transistors, 1,300 solid-state diodes, and had a power consumption of 150 watts. The machine did however make use of valves to generate its 125 kHz clock waveforms and in the circuitry to read and write on its magnetic drum memory, so it was not the first completely transistorised computer, a distinction that went to the Harwell CADET of 1955.
Problems with the reliability of early batches of transistors meant that the machine's mean time between failures was about 90 minutes, which improved once the more reliable junction transistors became available. The Transistor Computer's design was adopted by the local engineering firm of Metropolitan-Vickers in their Metrovick 950, in which all the circuitry was modified to make use of junction transistors. Six Metrovick 950s were built, the first completed in 1956. They were successfully deployed within various departments of the company and were in use for about five years.
Muse and AtlasEdit
Development of MUSE – a name derived from "microsecond engine" – began at the university in 1956. The aim was to build a computer that could operate at processing speeds approaching one microsecond per instruction, one million instructions per second. Mu (or µ) is a prefix in the SI and other systems of units denoting a factor of 10−6 (one millionth).
At the end of 1958 Ferranti agreed to collaborate with Manchester University on the project, and the computer was shortly afterwards renamed Atlas, with the joint venture under the control of Tom Kilburn. The first Atlas was officially commissioned on 7 December 1962, and was considered at that time to be the most powerful computer in the world, equivalent to four IBM 7094s. It was said that whenever Atlas went offline half of the UK's computer capacity was lost. Its fastest instructions took 1.59 microseconds to execute, and the machine's use of virtual storage and paging allowed each concurrent user to have up to one million words of storage space available. Atlas pioneered many hardware and software concepts still in common use today including the Atlas Supervisor, "considered by many to be the first recognisable modern operating system".
Two other machines were built: one for a joint British Petroleum/University of London consortium, and the other for the Atlas Computer Laboratory at Chilton near Oxford. A derivative system was built by Ferranti for Cambridge University, called the Titan or Atlas 2, which had a different memory organisation, and ran a time-sharing operating system developed by Cambridge Computer Laboratory.
The University of Manchester's Atlas was decommissioned in 1971, but the last was in service until 1974. Parts of the Chilton Atlas are preserved by the National Museums of Scotland in Edinburgh.
MU5 was designed to be about 20 times faster than Atlas, and was optimised for running compiled programs rather than hand-written machine code, something that contemporary computers were unable to do efficiently. A major factor in the MU5's much-improved performance over its predecessors was its incorporation of associative memory, which greatly speeded up access to its main store.
Work on MU5 started in 1966. The Science Research Council (SRC) awarded Manchester University a five-year grant of £630,466 in 1968 (equivalent to £9.3 million in 2016)[a] to develop the MU5, and ICL made its production facilities available to the university. Development began in 1969, and by 1971 the design team had grown from its initial nucleus of six members of the university's computer science department to 16, supported by 25 research students and 19 ICL engineers.
MU5 was fully operational by October 1974, coinciding with ICL's announcement that it was working on the development of a new range of computers, the 2900 series. ICL's 2980 in particular, first delivered in June 1975, owed a great deal to the design of MU5, which was in operation at the university until 1982.
MU5 was the last large-scale machine to be designed and built at Manchester University. The development of its successor, MU6, was funded by a grant of £219,300 awarded by the SRC in 1979 (equivalent to £890,000 in 2016).[a] MU6 was intended to be a range of processors with MU6-V at the top end and a personal processor, MU6-P, at the bottom. Only MU6-P and a mid-range processor, MU6-G, were ever produced, and ran between 1982 and 1987. The university did not have the resources to build the remaining machines in-house, and the system was never commercially developed.
SpiNNaker: Spiking Neural Network Architecture is a massively parallel, manycore supercomputer architecture designed by Steve Furber in the Advanced Processor Technologies Research Group (APT). It is composed of 57,600 ARM9 processors (specifically ARM968), each with 18 cores and 128 MB of mobile DDR SDRAM, totalling 1,036,800 cores and over 7 TB of RAM. The computing platform is based on spiking neural networks, useful in simulating the human brain (see Human Brain Project).
|Year||University Prototype||Year||Commercial Computer|
|1948||Manchester Baby, which evolved into the Manchester Mark 1||1951||Ferranti Mark 1|
|1953||Transistor computer||1956||Metrovick 950|
|1954||Manchester Mark II a.k.a. "Meg"||1957||Ferranti Mercury|
|1959||Muse||1962||Ferranti Atlas, Titan|
|1974||MU5||1974||ICL 2900 Series|
- Lavington (1998), p. 49
- Enticknap, Nicholas (Summer 1998), "Computing's Golden Jubilee", Resurrection, The Computer Conservation Society (20), ISSN 0958-7403, retrieved 19 April 2008
- Grimsdale, Dick, "50th Birthday of Transistor Computer", curation.cs.manchester.ac.uk, retrieved 24 February 2018
- "A Timeline of Manchester Computing", University of Manchester, archived from the original on 5 July 2008, retrieved 25 February 2009
- The Virtual Museum of Manchester Computing: Timeline of Manchester Computing
- Lavington (1998), p. 7
- Lavington (1998), p. 21
- Lavington, Simon (1980), Early British Computers, Manchester University Press, ISBN 978-0-7190-0803-0
- Lavington, Simon (1998), A History of Manchester Computers (2nd ed.), The British Computer Society, ISBN 978-1-902505-01-5
- Napper, R. B. E. (2000), "The Manchester Mark 1 Computers", in Rojas, Raúl; Hashagen, Ulf (eds.), The First Computers: History and Architectures, MIT Press, pp. 356–377, ISBN 978-0-262-68137-7
- Tootill, Geoff (Summer 1998), "The Original Original Program", Resurrection, The Computer Conservation Society (20), ISSN 0958-7403, retrieved 19 April 2008
- Manchester Museum of Science & Industry (2011), "The "Baby": The World's First Stored-Program Computer" (PDF), MOSI, retrieved 3 April 2012
- "Electronic Digital Computers", Nature, 162: 487, 25 September 1948, doi:10.1038/162487a0, archived from the original on 6 April 2009, retrieved 22 January 2009
- Napper (2000), p. 365
- Lavington (1998), p. 17
- Napper, R. B. E., "The Manchester Mark 1", University of Manchester, archived from the original on 9 February 2014, retrieved 22 January 2009
- Lavington, S. H. (July 1977), "The Manchester Mark 1 and Atlas: a Historical Perspective" (PDF), University of Central Florida, retrieved 8 February 2009. (Reprint of the paper published in Communications of the ACM (January 1978) 21 (1)
- Lavington (1998), p. 18
- Lavington (1998), p. 31
- Lavington (1998), pp. 34–35
- Lavington (1998), p. 37
- "COMPUTERS, Overseas: 5. Manchester University - A SMALL EXPERIMENTAL TRANSISTOR DIGITAL COMPUTER". 7 (2). April 1955: 16–17.
- Cooke-Yarborough, E. H. (June 1998), "Some early transistor applications in the UK", Engineering and Science Education Journal, IEE, 7 (3): 100–106, doi:10.1049/esej:19980301, ISSN 0963-7346, retrieved 7 June 2009 (subscription required)
- Lavington (1998), pp. 36–37
- "The Atlas", University of Manchester, archived from the original on 28 July 2012, retrieved 21 September 2010
- Lavington (1998), p. 41
- Lavington (1998), pp. 44–45
- Lavington (1980), pp. 50–52
- Lavington (1998), p. 43
- Lavington (1998), p. 44
- Lavington (1998), pp. 46–47
- Lavington (1998), pp. 47–48
- Lavington (1998), pp. 48–49
- "50 Years of Computing at Manchester", University of Manchester, retrieved 17 September 2010
- IEEE Annals of the History of Computing, 21, IEEE Computer Society, 1999
- Advanced Processor Technologies Research Group
- "SpiNNaker Project - The SpiNNaker Chip". apt.cs.manchester.ac.uk. Retrieved 17 November 2018.
- SpiNNaker Home Page, University of Manchester, retrieved 11 June 2012
- Furber, S. B.; Galluppi, F.; Temple, S.; Plana, L. A. (2014). "The SpiNNaker Project". Proceedings of the IEEE. 102 (5): 652–665. doi:10.1109/JPROC.2014.2304638.
- Xin Jin; Furber, S. B.; Woods, J. V. (2008). "Efficient modelling of spiking neural networks on a scalable chip multiprocessor". 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence). pp. 2812–2819. doi:10.1109/IJCNN.2008.4634194. ISBN 978-1-4244-1820-6.
- A million ARM cores to host brain simulator News article on the project in the EE Times
- Temple, S.; Furber, S. (2007). "Neural systems engineering". Journal of the Royal Society Interface. 4 (13): 193–206. doi:10.1098/rsif.2006.0177. PMC 2359843. PMID 17251143. A manifesto for the SpiNNaker project, surveying and reviewing the general level of understanding of brain function and approaches to building computer modelof the brain.
- Plana, L. A.; Furber, S. B.; Temple, S.; Khan, M.; Shi, Y.; Wu, J.; Yang, S. (2007). "A GALS Infrastructure for a Massively Parallel Multiprocessor". IEEE Design & Test of Computers. 24 (5): 454. doi:10.1109/MDT.2007.149. A description of the Globally Asynchronous, Locally Synchronous (GALS) nature of SpiNNaker, with an overview of the asynchronous communications hardware designed to transmit neural 'spikes' between processors.
- Navaridas, J.; Luján, M.; Miguel-Alonso, J.; Plana, L. A.; Furber, S. (2009). "Understanding the interconnection network of SpiNNaker". Proceedings of the 23rd international conference on Conference on Supercomputing - ICS '09. p. 286. CiteSeerX 10.1.1.634.9481. doi:10.1145/1542275.1542317. ISBN 9781605584980. Modelling and analysis of the SpiNNaker interconnect in a million-core machine, showing the suitability of the packet-switched network for large-scale spiking neural network simulation.
- Rast, A.; Galluppi, F.; Davies, S.; Plana, L.; Patterson, C.; Sharp, T.; Lester, D.; Furber, S. (2011). "Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware". Neural Networks. 24 (9): 961–978. doi:10.1016/j.neunet.2011.06.014. PMID 21778034. A demonstration of SpiNNaker's ability to simulate different neural models (simultaneously, if necessary) in contrast to other neuromorphic hardware.
- Sharp, T.; Galluppi, F.; Rast, A.; Furber, S. (2012). "Power-efficient simulation of detailed cortical microcircuits on SpiNNaker". Journal of Neuroscience Methods. 210 (1): 110–118. doi:10.1016/j.jneumeth.2012.03.001. PMID 22465805. Four-chip, real-time simulation of a four-million-synapse cortical circuit, showing the extreme energy efficiency of the SpiNNaker architecture