This article may be too technical for most readers to understand.(June 2020)
AArch64 or ARM64 is the 64-bit extension of the ARM architecture family.
Armv8.x and Armv9.x extensions and featuresEdit
Announced in October 2011, Armv8-A represents a fundamental change to the ARM architecture. It adds an optional 64-bit architecture, named "AArch64", and the associated new "A64" instruction set. AArch64 provides user-space compatibility with the existing 32-bit architecture ("AArch32" / Armv7-A), and instruction set ("A32"). The 16-32bit Thumb instruction set is referred to as "T32" and has no 64-bit counterpart. Armv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor. ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012. Apple was the first to release an Armv8-A compatible core (Cyclone) in a consumer product (iPhone 5S). AppliedMicro, using an FPGA, was the first to demo Armv8-A. The first Armv8-A SoC from Samsung is the Exynos 5433 used in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it will run only in AArch32 mode.
- 64 + 32 bit
- Architecture: AArch64
- Specification: Armv8-A
- Instruction sets: A64 + A32
- Suffixes: v8-A
- 32 + 16 (Thumb) bit
- Architecture: AArch32
- Specification: Armv8-R / Armv7-A
- Instruction sets: A32 + T32
- Suffixes: -A32 / -R / v7-A
- Example: Armv8-R, Cortex-A32
- New instruction set, A64
- Has 31 general-purpose 64-bit registers.
- Has dedicated zero or stack pointer (SP) register (depending on instruction).
- The program counter (PC) is no longer directly accessible as a register.
- Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped).
- Has paired loads/stores (in place of LDM/STM).
- No predication for most instructions (except branches).
- Most instructions can take 32-bit or 64-bit arguments.
- Addresses assumed to be 64-bit.
- Advanced SIMD (Neon) enhanced
- A new exception system
- Fewer banked registers and modes.
- Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension (LPAE), which was designed to be easily extended to 64-bit.
Extension: Data gathering hint (Armv8.0-DGH)
AArch64 was introduced in Armv8-A and is included in subsequent versions of Armv8-A. It was also introduced in Armv8-R as an option, after its introduction in Armv8-A; it is not included in Armv8-M.
The main opcode for selecting which group an A64 instruction belongs to is at bits 25-28.
|Reserved||op0||0000||op1||Immediate constant 16 bits|
|Data Processing — Immediate PC-rel.||op||immlo||10000||immhi||Rd|
|Data Processing — Immediate Others||sf||100||01-11||Rd|
|Branches + System Instructions||op0||101||op1||op2|
|Load and Store Instructions||op0||1||op1||0||op2||op3||op4|
|Data Processing — Register||sf||op0||op1||101||op2||op3|
|Data Processing — Floating Point and SIMD||op0||111||op1||op2||op3|
In December 2014, Armv8.1-A, an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation.
Instruction set enhancements included the following:
- A set of AArch64 atomic read-write instructions.
- Additions to the Advanced SIMD instruction set for both AArch32 and AArch64 to enable opportunities for some library optimizations:
- Signed Saturating Rounding Doubling Multiply Accumulate, Returning High Half.
- Signed Saturating Rounding Doubling Multiply Subtract, Returning High Half.
- The instructions are added in vector and scalar forms.
- A set of AArch64 load and store instructions that can provide memory access order that is limited to configurable address regions.
- The optional CRC instructions in v8.0 become a requirement in Armv8.1.
Enhancements for the exception model and memory translation system included the following:
- A new Privileged Access Never (PAN) state bit provides control that prevents privileged access to user data unless explicitly enabled.
- An increased VMID range for virtualization; supports a larger number of virtual machines.
- Optional support for hardware update of the page table access flag, and the standardization of an optional, hardware updated, dirty bit mechanism.
- The Virtualization Host Extensions (VHE). These enhancements improve the performance of Type 2 hypervisors by reducing the software overhead associated when transitioning between the Host and Guest operating systems. The extensions allow the Host OS to execute at EL2, as opposed to EL1, without substantial modification.
- A mechanism to free up some translation table bits for operating system use, where the hardware support is not needed by the OS.
- Top byte ignore for memory tagging.
In January 2016, Armv8.2-A was announced. Its enhancements fell into four categories:
- Optional half-precision floating-point data processing (half-precision was already supported, but not for processing, just as a storage format.)
- Memory model enhancements
- Introduction of Reliability, Availability and Serviceability Extension (RAS Extension)
- Introduction of statistical profiling
Scalable Vector Extension (SVE) Edit
The Scalable Vector Extension (SVE) is "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization of high-performance computing scientific workloads. The specification allows for variable vector lengths to be implemented from 128 to 2048 bits. The extension is complementary to, and does not replace, the NEON extensions.
A 512-bit SVE variant has already been implemented on the Fugaku supercomputer using the Fujitsu A64FX ARM processor. It aims to be the world's highest-performing supercomputer with "the goal of beginning full operations around 2021."
SVE is supported by the GCC compiler, with GCC 8 supporting automatic vectorization and GCC 10 supporting C intrinsics. As of July 2020, LLVM and clang support C and IR intrinsics. ARM's own fork of LLVM supports auto-vectorization.
In October 2016, Armv8.3-A was announced. Its enhancements fell into six categories:
- Pointer authentication (AArch64 only); mandatory extension (based on a new block cipher, QARMA) to the architecture (compilers need to exploit the security feature, but as the instructions are in NOP space, they are backwards compatible albeit providing no extra security on older chips).
- Nested virtualization (AArch64 only)
- Advanced SIMD complex number support (AArch64 and AArch32); e.g. rotations by multiples of 90 degrees.
- A change to the memory consistency model (AArch64 only); to support the (non-default) weaker RCpc (Release Consistent processor consistent) model of C++11/C11 (the default C++11/C11 consistency model was already supported in previous Armv8).
- ID mechanism support for larger system-visible caches (AArch64 and AArch32)
- "SHA3 / SHA512 / SM3 / SM4 crypto extensions"
- Improved virtualization support
- Memory Partitioning and Monitoring (MPAM) capabilities
- A new Secure EL2 state and Activity Monitors
- Signed and unsigned integer dot product (SDOT and UDOT) instructions.
- Memory Tagging Extension (MTE)
- Branch Target Indicators (BTI) to reduce "the ability of an attacker to execute arbitrary code",
- Random Number Generator instructions – "providing Deterministic and True Random Numbers conforming to various National and International Standards"
- Scalable Vector Extension 2 (SVE2). SVE2 builds on SVE's scalable vectorization for increased fine-grain Data Level Parallelism (DLP), to allow more work done per instruction. SVE2 aims to bring these benefits to a wider range of software including DSP and multimedia SIMD code that currently use Neon. The LLVM/Clang 9.0 and GCC 10.0 development codes were updated to support SVE2.
- Transactional Memory Extension (TME). Following the x86 extensions, TME brings support for Hardware Transactional Memory (HTM) and Transactional Lock Elision (TLE). TME aims to bring scalable concurrency to increase coarse-grained Thread Level Parallelism (TLP), to allow more work done per thread. The LLVM/Clang 9.0 and GCC 10.0 development codes were updated to support TME.
- Confidential Compute Architecture (CCA)
- Scalable Matrix Extension (SME). SME adds new features to process matrices efficiently, such as:
- Matrix tile storage
- On-the-fly matrix transposition
- Load/store/insert/extract tile vectors
- Matrix outer product of SVE vectors
- "Streaming mode" SVE
In September 2019, Armv8.6-A was announced. It adds:
- General Matrix Multiply (GEMM)
- Bfloat16 format support
- SIMD matrix manipulation instructions, BFDOT, BFMMLA, BFMLAL and BFCVT
- enhancements for virtualization, system management and security
- and the following extensions (that LLVM 11 already added support for):
- Enhanced Counter Virtualization (Armv8.6-ECV)
- Fine-Grained Traps (Armv8.6-FGT)
- Activity Monitors virtualization (Armv8.6-AMU)
For example, fine-grained traps, Wait-for-Event (WFE) instructions, EnhancedPAC2 and FPAC. The Bfloat16 extensions for SVE and Neon are mainly for deep learning use.
- Enhanced support for PCIe hot plug (AArch64)
- Atomic 64-byte load and stores to accelerators (AArch64)
- Wait For Instruction (WFI) and Wait For Event (WFE) with timeout (AArch64)
- Branch-Record recording (Armv9.2 only)
- Non-maskable interrupts (AArch64)
- Instructions to optimize memcpy() and memset() style operations (AArch64)
- Enhancements to PAC (AArch64)
- Hinted conditional branches (AArch64)
Armv8-R (real-time architecture)Edit
This section needs expansion with: examples and additional citations. You can help by adding to it. (May 2021)
Optional AArch64 support was added to the Armv8-R profile, with the first Arm core implementing it being the Cortex-R82. It adds the A64 instruction set, with some changes to the memory barrier instructions.
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