Tensilica(Redirected from Xtensa)
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Tensilica was a company based in Silicon Valley in the semiconductor intellectual property core business. It is now a part of Cadence Design Systems. Its dataplane processors (DPUs) combine the strengths of CPUs and DSPs and custom logic with 10 to 100 times the performance, making them suited for data-intensive processing tasks.
|Industry||Semiconductor intellectual property core|
|Headquarters||San Jose, California|
|Chris Rowen, Jack Guedj|
|Products||Microprocessors, Hifi audio, DSP cores|
Tensilica is known for its customizable microprocessor core, the Xtensa configurable processor. Other products include: HiFi audio/voice DSPs with a software library of over 225 codecs from Cadence and over 100 software partners; Vision DSPs that handle complex algorithms in imaging, video, computer vision, and neural networks; and ConnX family of baseband DSPs ranging from the dual-MAC ConnX D2 to the 64-MAC ConnX BBE64EP.
Tensilica was founded in 1997 by Chris Rowen (one of the founders of MIPS Technologies) and was initially staffed by former employees of several other Silicon Valley processor and electronic design automation companies. It employed Earl Killian, who contributed to the MIPS architecture, as chief software architect for several years. On March 11, 2013, Cadence Design Systems announced its intent to buy Tensilica for approximately $380 million in cash. Cadence completed the acquisition in April 2013, with a cash outlay at closing of approximately $326 million. 
Cadence Tensilica productsEdit
Cadence Tensilica develops SIP blocks to be included on the chip (IC) designs of products of their licensees, such as system on a chips for embedded systems, particularly in mobile, home entertainment, and communications. Tensilica processors are delivered as synthesizable RTL for easy integration into chip designs.
Xtensa configurable coresEdit
An Xtensa processor can be customized into anything from a small, low-power cache-less microcontroller to a high-performance 16-way SIMD processor, 3-issue VLIW DSP core, or a 1 TMAC/sec neural network processor. All Cadence standard DSPs are based on the Xtensa architecture.
IP processor vendors such as Tensilica typically offer their licensees the choice between many of the IP core's implementation details: cache size, processor bus width, data and instruction RAMs, memory management and interrupt control. However, Cadence's Xtensa architecture offers a key differentiating feature, a user-customizable instruction set.
Using the supplied customization tools, customers can extend the Xtensa base instruction set by adding new user-defined instructions. Extensions can include SIMD instructions, new register files, and additional data transfer interfaces for multiprocessor communication. After the final processor configuration is made and submitted, the Tensilica processor generator service builds the configured Xtensa IP core, processor design kit, and software development kit. This process is highly automated so designers can quickly experiment with different instruction additions, testing the performance improvements and power trade-offs of the various alternatives.
The processor kit contains items necessary to integrate the configured IP into the customer's chip design environment: the core's hardware description (in synthesizeable RTL or physical post-layout form), timing & I/O constraints, requirements for technology-specific RAMs/caches/FIFOs. The software kit is built on the Eclipse-based integrated development environment, and uses a GNU Compiler Collection-derived tool-chain: C/C++ compiler, assembler, linker, debugger. An instruction set simulator enables customers to begin application development before actual hardware is available.
Xtensa instruction setEdit
The Xtensa instruction set is designed to meet the diverse requirements of dataplane processing. This 32-bit architecture features a compact 16- and 24-bit instruction set with modeless switching for maximum power efficiency and performance. The base instruction set has 80 RISC instructions and includes a 32-bit ALU, up to 64 general-purpose 32-bit registers, and six special-purpose registers.
HiFi Audio and Voice DSP IPEdit
- HiFi Mini Audio DSP — The smallest, lowest power DSP core for always-listening voice trigger and voice recognition
- HiFi 2 Audio DSP — This highly efficient DSP core provides the lowest power MP3 audio processing
- HiFi EP Audio DSP — A superset of HiFi 2 with advanced optimizations for DTS Master Audio, improved voice pre- and post-processing, and improved cache memory subsystem
- HiFi 3 Audio DSP — Full 32-bit processing makes this DSP super efficient for many of the audio enhancement algorithms, wideband voice codecs, and multi-channel audio
- HiFi 3z Audio DSP — More energy efficient for object-based audio, super-wideband voice codecs, and neural-network-based automatic speech recognition.
- HiFi 4 DSP - 2X HiFi 3 performance for DSP intensive applications including emerging multi-channel object-based audio standards.
- Vision P5 DSP, which offers 4–100x the performance relative to traditional mobile CPU+GPU systems at a fraction of the power/energy.
- Vision P6 DSP, with 4X the peak performance of the Vision P5 DSP for demanding image and computer vision applications.
- Vision C5 DSP, with 1 TMAC/sec computational capacity to run all neural network computational tasks without the need for additional hardwired accelerators.
Microsoft HoloLens uses special custom-designed TSMC-fabricated 28nm coprocessor that has 24 Tensilica DSP cores. It has around 65 million logic gates, 8 MB of SRAM, and an additional layer of 1 GB of low-power DDR3 RAM.
Espressif ESP8266 Wi-Fi IoT SoC integrates the Tensilica Diamond Standard 106Micro 32-bit controller processor core, which Espressif calls L106.
Spreadtrum licensed the HiFi DSP for smartphones
VIA Technologies uses a HiFi DSP in an SoC for set top box, tablets, and mobile devices.
Realtek standardized on the HiFi Audio DSP for mobile and PC products.
Over 80 top-tier semiconductor companies and system OEM customers use HiFi audio DSPs in their chip designs.
- In 1997 Tensilica was founded by Chris Rowen.
- In 2002 Tensilica released support for flexible length instruction encodings, known as FLIX.
- In 2013 Cadence Design Systems acquired Tensilica.
- "Technical Advisory Board". Stretch. 2010-11-26. Retrieved 2010-11-26.
Earl ... He is the former Chief Architect of Tensilica and Silicon Graphics MIPS division, ...
- "Cadence to Acquire Tensilica."
- Source: http://ip.cadence.com/news/432/330/Cadence-Reports-First-Quarter-2013-Financial-Results-and-Completes-Acquisition-of-Tensilica
- "Everything You Wanted to Know About AMD TrueAudio". Maximum PC. 2013-10-08. Archived from the original on July 11, 2014. Retrieved 2014-07-06.