Arithmetic
editCLZ
editCounting Leading Zero
always @* begin
clz[4] = src[31:16] == 16'd0;
clz[3] = pat16[15:8] == 8'd0;
clz[2] = pat8[ 7:4] == 4'd0;
clz[1] = pat4[ 3:2] == 2'd0;
clz[0] = !pat2[ 1];
end
always @* begin
pat16 = clz[4] ? src[15:0] : src[31:16];
pat8 = clz[3] ? pat16[ 7:0] : pat16[15: 8];
pat4 = clz[2] ? pat8[ 3:0] : pat8[ 7: 4];
pat2 = clz[1] ? pat4[ 1:0] : pat4[ 3: 2];
end
IEEE 754 half-precision
editExponent
editexponent = exp + 15 (range: 0~30, 0 for denormalization), Examples:
- exponent(2-14) = -14 + 15 = 1
- exponent(20) = 0 + 15 = 15
- exponent(215) = 15 + 15 = 30
Mantissa
edit- Normalization: Most significant 10-digit mantissa
- de-Normalization: 10-digital mantissa in base of 2-14
- ex: 2-16 = .01e-14, Mantissa = 10016
Half precision examples
editSignbit Exponent10 Mantissa
- 0 3010 11111111112 = 7bff16 = 215 × (1 + (1 − 2−10)) = 65504
(largest normal number)
- 0 1510 00000000012 = 3c0116 = 1 + 2−10 ≈ 1.001
(smallest number larger than one)
Verilog-mode
edit.vimrc
editset hlsearch
set softtabstop=8
set backspace=indent,eol,start
set autoindent
set nocompatible
syntax on
...
source ~/verilog_emacsauto.vim
STEP
edit- move verilog-mode.el under ~/elisp
- add (setq enable-local-eval t) to verilog-mode.el::1
- cp v-emacsauto.vim to ~/emacsauto.vim
- source emacsauto.vim in .vimrc
How to Use
edit- \+d to delete autos
- \+a to expand autos
Example
editmodule $MODULE (
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);
//--------------------------------------------------------//
// Function
//--------------------------------------------------------//
function integer clog2;
input [31:0] value;
integer i;
begin
clog2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clog2 = i + 1;
end
endfunction
//--------------------------------------------------------//
// Parameter
//--------------------------------------------------------//
localparam
//--------------------------------------------------------//
// Declaration
//--------------------------------------------------------//
/*AUTOWIRE*/
//--------------------------------------------------------//
// Assignment
//--------------------------------------------------------//
//--------------------------------------------------------//
// Debug flag
//--------------------------------------------------------//
/*gldc AUTO_TEMPLATE (
.DW (16),
);*/
gldc
#(/*AUTOINSTPARAM*/)
gldc
(/*AUTOINST*/);
/*tof_debug AUTO_TEMPLATE (
.debug_00 ({4'd0}),
.debug_[0-9]. ({@"vl-width"{1'b0}}),
.debug_flag (debug_flag[]),
);*/
endmodule
/*qua_ctcp_mac_rx_pack AUTO_TEMPLATE "_mac\([0-7]\)" (
.clk (clk1600),
//-- reset
.\(rst_.*\)_ppr_mac_\(.*\) (\1_ppr@"(/ @ 2)"_mac@"(% @ 2)"_\2[]), //-- RST.PRB
.\(rst_.*\)_mac_\(.*\) (\1_mac@_\2[]), //-- RST.others
//-- param
.DWIDTH_\(.*\)_PPR_MAC_\(.*\) (`QUA_IOS_CTCP_\1_PPR@"(/ @ 2)"_MAC@"(% @ 2)"_\2_SZ), //-- param.PRB
.DWIDTH_\(.*\)_MAC_\(.*\) (`QUA_IOS_CTCP_\1_MAC@_\2_SZ), //-- param.others
//-- data
.\(rxp_prb\)_ppr_mac_\(.*\) (\1_ppr@"(/ @ 2)"_mac@"(% @ 2)"_\2[]), //-- rxp.PRB
.\(dwa_prb\)_ppr_mac_\(.*\) (\1_ppr@"(/ @ 2)"_mac@"(% @ 2)"_\2[]), //-- dwa.PRB
.\(rxp.*\)_mac_\(.*\) (\1_mac@_\2[]), //-- rxp.others
.\(dwa.*\)_mac_\(.*\) (\1_mac@_\2[]), //-- dwa.others
);*/
/*nu_fifo_async AUTO_TEMPLATE "afifo_\(.*\)" (
.test_mode (ss_ctcp_TEST__CLK_GATE_DISABLE),
//-- wr
.clk_wr (clk1600),
.rst_wr (rst), // FIX_ME
.wdata (rxp_@_wdata[]),
.wen (rxp_@_wen),
.full (dmy_rxp_@_full),
.almostfull (dmy_rxp_@_almostfull),
//-- rd
.clk_rd (clk1450),
.rst_rd (rst), // FIX_ME
.ren (rxf_@_ren),
.empty (rxf_@_empty),
.rdata (rxf_@_rdata[]),
);*/
/*
Local Variables:
verilog-auto-inst-param-value: t
verilog-library-flags:("-f $LIST.f")
verilog-auto-output-ignore-regexp: ""
eval:(setq verilog-auto-output-ignore-regexp (concat
"^\\("
"\\|reg.*"
"\\|dmy.*"
"\\)$"
))
End:
*/
Automation
editExcel to XML
edithttps://www.ibm.com/developerworks/cn/xml/x-tipexc/index.html#artrelatedtopics
Phtyon
edit- Example
fixpoint = 4
# Open the file
f = open('data/TOFBlockSize.txt')
blksize = f.readline().split('\n')
blksize = blksize[0]
print 'blksize: %s' % blksize
f.close()
# Open the file
f = open('data/TOFroi.txt')
x0 = f.readline().split('\n')
y0 = f.readline().split('\n')
xblk = f.readline().split('\n')
yblk = f.readline().split('\n')
x0=x0[0]
y0=y0[0]
xblk=xblk[0]
yblk=yblk[0]
print(x0)
print(y0)
print(xblk)
print(yblk)
f.close()
srl_val = int(blksize) *2 - 2 - fixpoint
rnd_val = int(round(2**(srl_val-1)-0.5))
print 'srl_val: %s' % srl_val
print 'rnd_val: %s' % rnd_val
file = open('dut.par','w')
file.write('parameter GOLDEN_COMPARE = 1\'b1;\n')
file.write('parameter REGSTOPERR = 1\'b1;\n')
file.write('//==================\n')
file.write('parameter HEX_IMGTXT = 0;\n')
file.write('parameter TOF_TEST_SRC = 0;\n')
file.write('parameter FRAME_HEIGHT = 1308;\n')
file.write('parameter FRAME_WIDTH = 768;\n')
file.write('parameter TOF_LOG_BLOCK_SIZE = ' + blksize + ';\n')
file.write('parameter TOF_BLOCK_SRL_VAL = ' + str(srl_val) + ';\n')
file.write('parameter TOF_BLOCK_RND_VAL = ' + str(rnd_val) + ';\n')
file.write('parameter TOF_ROI_X0_IDX = ' + x0 + ';\n')
file.write('parameter TOF_ROI_Y0_IDX = ' + y0 + ';\n')
file.write('parameter TOF_BLOCK_NUM_X = ' + xblk + ';\n')
file.write('parameter TOF_BLOCK_NUM_Y = ' + yblk + ';\n')
file.close()
XML example
edit<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<module XLS="TOF.xls">
<address radix="HEX" type="ABSOLUTE">0x3000</address>
<name>TOF</name>
<description></description>
<documentation></documentation>
<user-defined>
<CPP_Module_name>CPP1</CPP_Module_name>
<module_hier>top</module_hier>
</user-defined>
<register>
<address radix="HEX" type="RELATIVE">0x000</address>
<name>TOF_RO</name>
<width>32</width>
<count></count>
<description></description>
<Documentation></Documentation>
<user-defined>
<Documentation></Documentation>
</user-defined>
<field>
<position>0</position>
<name>VERSION_CODE</name>
<access>RO</access>
<visibility>PUBLIC</visibility>
<default-value>16'd0</default-value>
<description></description>
<documentation></documentation>
<width>16</width>
<user-defined>
<Format></Format>
<MNE></MNE>
<Hidden_Enum></Hidden_Enum>
<SIGNSEL></SIGNSEL>
<TAG></TAG>
<Double_Buffer></Double_Buffer>
<C_Enum></C_Enum>
</user-defined>
</field>
</register>
Assertion
editImmediate
editAn immediate assertion is a test of an expression the moment the statement is executed SYNTAX: [name:] assert (expression) [pass_statement] [else fail_statement]
always @(state)
assert (state == $onehot) else $fatal;
Concurrent
edit a_reqack: assert property (
@(posedge clk) req ##[1:3] ack; )
else $error("ack not within 1~3 cycles after req");
`ifndef VERILATOR
// there should never be a grant when there is no request
assert property (
@(posedge clk) (instr_gnt_i) |-> (instr_req_o) )
else $warning("There was a grant without a request");
`endif
Example
editassert property (@(posedge clk) disable iff(!reset_) not $isunknow(....))
else $fatal("message hear");
(* category = 1 *) sva_never_ctcp0_ccmx_tx_cntra_BUNDLE_is_X :
assert property (
@(posedge clk)
disable iff($sampled(local_rst))
~((^({1'b0, ctcp0_ccmx_tx_cntra_data})===1'bx))
) else $display("SVA Error: ((^({1'b0, ctcp0_ccmx_tx_cntra_data})===1'bx)) should always be false");
(* category = 1 *) sva_never_0 :
assert property (
@(posedge clk_wr)
disable iff(rst_wr!==1'b0)
~((wen===1'b1 && full===1'b1))
) else $display("SVA Error: ((wen===1'b1 && full===1'b1)) should always be false");
(* category = 1 *) sva_never_1 :
assert property (
@(posedge clk_rd)
disable iff(rst_rd!==1'b0)
~((ren===1'b1 && empty===1'b1))
) else $display("SVA Error: ((ren===1'b1 && empty===1'b1)) should always be false");
`ifdef NAXI_ASSERT_END_OF_SIMULATION
wire rst_rd_assert = rst_rd !== 1'b0;
quiescence_at_EOS_clk: assert property ( @(posedge clk_rd) disable iff (rst_rd_assert)
$rose(`NAXI_ASSERT_END_OF_SIMULATION) |-> (empty===1'b1)
) else $display($stime, ": ERROR: %m");
`endif
Reference
edit- https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/
- https://www.design-reuse.com/articles/10907/using-systemverilog-assertions-in-rtl-code.html
- http://www.sutherland-hdl.com/papers/2006-DesignCon_Getting_Started_with_SVA_presentation.pdf
- http://www.cse.scu.edu/~mwang2/verification/Sva.pdf
Netlister
editExamples
editTo Generate a module: --------------------- netlister -gen_module qsx
To Generate a module (and expand the RTL files only): --------------------- netlister -gen_module qsx -rtl
To Generate a module (and expand the DV files only): --------------------- netlister -gen_module qsx -dv
To expand the DV files only --------------------- netlister -gen_tb qsx
To Generate a stubbed module: ----------------------------- netlister -gen_module aca -output_path . -stub
To Generate a stubbed module (without the DV interfaces): ----------------------------- netlister -output_path . -stub -gen_module bax -gen_if 0
To Generate a cluster or the netlist based on an .mrl file (and use all stubbed blocks in a local directory, without generating verification interfaces): ----------------------------- netlister -mrl ${PROJ_SRC_ROOT}/quadpeaks/qua_netlist.mrl -gen_netlist -emacs_expand -use_stubs -output_path . -no_default_libs -gen_if 0
Useful Tips
editGenerate
editgenvar i;
generate
for (i=0 ; i<P_STAGES; i++) begin: reset_pipeline_stages_unroll
if( i==0 )
always_ff @(posedge clk)
rst__pipe[i] <= rst;
else
always_ff @(posedge clk)
rst__pipe[i] <= rst__pipe[i-1];
end // for i
endgenerate
HLS
editBasic
edit- What: High-level synthesis (HLS), sometimes referred to as C synthesis is an automated design process that interprets an algorithmic description of a desired Hardward behavior and creates circuits that implements that behavior.
- Why: The increasing complexity of logic design in recent decades has forced the methodologies and tools to move to higher abstraction levels. Simulation process in RTL is much inefficient than that in hardware behavior description such as using C for the programming inherent natural.
Deep Learning
editSVM
editCUDA
editTensorFlow
editFMCW
editDepth Imaging
editEDA
editVerdi
edithttp://www.ictown.com/thread-108024-1-1.html
https://wenku.baidu.com/view/a7a5fcbca32d7375a517800b.html
Version Code
edit#! /bin/bash
if [ ! -f changelist.txt ]; then
echo "changelist.txt not found!"
exit
fi
echo "commit log ..."
cat changelist.txt
svn up
svn_ver=$(svn info | grep '^Revision:' | sed -e 's/^Revision: //g')
svn_ver=$((svn_ver+1))
echo "svn ver: $svn_ver"
# version replacement
echo "SVN version update..."
perl -pi -e "s/SVN_VERSION 16'h.*/SVN_VERSION 16'h$svn_ver/g" rtl/tof_define.v
svn ci -F changelist.txt
Async reset
edithttp://www.gstitt.ece.ufl.edu/courses/spring17/eel4712/labs/CummingsSNUG2002SJ_Resets.pdf
// armcm0, tbench
// Synchronize AHB reset, and factor in reset request from the CPU
reg [1:0] rst_sync;
always @(posedge sim_clock or negedge power_on_reset_n)
if(!power_on_reset_n)
rst_sync <= 2'b00;
else
rst_sync <= {rst_sync[0],~SYSRESETREQ};
Scripts
editcshell
editset autolist = ambiguous
set complete = enhance
run.sh
edit#! /bin/tcsh -f
set pat_dir = "pat"
if ( "$1" == "" ) then
echo "error! pattern name is required!\n"
exit 0
else
set pat_name = "$1"
echo "pattern name: $pat_name"
endif
if (-e simulation.pat) then
rm simulation.pat
endif
if (-e ./fsdb/${pat_name}.fsdb) then
rm ./fsdb/${pat_name}.fsdb
endif
if (! -e ./${pat_dir}/${pat_name}.pat) then
echo "error! pattern ${pat_dir}/${pat_name}.pat not exists\n"
exit 0
else
cp ./${pat_dir}/${pat_name}.pat ./simulation.pat
endif
if (! -d fsdb) then
mkdir fsdb
endif
verdi.sh
editMakefile
editverdi:
expand_vf_file -y -e '$CFG=""' rtl.vf | tee all.f
TB
editCDE
editMISC
edit- Path: analog macro, memory macro...
LEC
edit- make script:
Workstation
edit
bjobs -u all -q $cmdq
Conformal LEC
editHow to
edit- Create a snapshot
- Macro EQ?
- Mapping key point
Script
editset log file $LOGFILE -replace
set undefined cell error -both
set parallel option -license xl -max_threads 4
set hdl option -skip_unnamed_blk_naming on
set naming rule "%L_%s" "%L_%d__%s" "%s" -instance
//read in library and design
read library
read design -define
report design data
report black box -class full -both -detail
// constraints
add primary input $NETPATH -Net -Cut -revised
add pin constraint 0 $NETPATH -revised
// flatten model
set flatten model -seq_constant
set mapping method -name only
// Compare
set root module $ROOTMODULE -golden
set root module $ROOTMODULE -revised
set system mode lec
add compared points -all
compare -NONEQ_Print -NONEQ_stop 1
// Hierarchical compare
Conformal ECO
editIntroduction
edit- Conformal ECO is based on formal EC for finding the NON-EQ key point and internally equivalent point (NET).
- Benefits:
Flattened Flow
edit- Manually ECO for registers changes (added/deleted/renamed)
- Register D: scan-chain ECO, i.e., bypass D in scan flow. Cell must be kept in the netlist to prevent net re-naming issue by Conformal ECO.
- Register R: cell rename, but type, netlist must be kept.
- Register A: dealing with CG*.
- Copy cells netlist from G2, including clock gating cell (CG*)
- re-mapping ports .CK, .RB, .D, etc.,.
- Grep all not-mapped key point to determine what DFF/DLAT should be manually ECOed
- Run conformal ECO, set flatten model without -GATED_CLOCK.
- Write ECO design with cell report.
Cons/Pros
edit- Because flattened, Conformal ECO not supports automation module-by-module. You may do it by yourself.
- Be award of clock balancing on added DFF. Flatten model with -NOGATED_CLOCK (default) is suggested.
- Flattened flow deals with false NON-EQ issue, easy to simply scripts with no boundary constraint.
- Hier ECO needs add_pin_constraint which could be extracted by analyze hier_compare
- Flattened flow may generate poor quality of ECO patch.
Some Tips
edit- Must using NAME ONLY mapping method to ensure minimal key-point match.
- Deal with clock gating, use -NOGATED_CLOCK option instead. Otherwise, conformal ECO will replace clock net from middle-tree node.
- Report unmapped PI/PO
- Report not-mapped key point
Flattened
editread library
read design $G1 -Verilog -Golden
read design $G2 -Verilog -Revised
report design data
report black box
set flatten model -eco
set flatten model -enable_analyze_hier_compare
set eco option -flat
flatten -nolibrary -matchhierarchy -revised
uniquify -all -rev -nolib
set system mode setup
// add pin constraint
set mapping method -name only
set system mode lec
report key point -unmapped -type PI -both
report key point -unmapped -type PO -both
report unmapped point -notmapped
analyze set -cut -verbose
analyze hier_compare -dofile flatten_eco.hier.dofile \
-eco_aware \
-noexact_pin_match \
-constraints -input_output_pin_equivalence -function_pin_mapping \
-threshold 0 \
-verbose \
-replace
add compared point -all
compare -NONEQ_print
compare eco hierarchy -verbose
report eco hierarchy -noneq -verbose
report compare -data -sum
report black box
Verification
editADiT: Analog/Digital Co-sim
editFile for ADiT-VPI/ADiT-HDL
- cosim.f: cosim file list
- analog.f: include model, etc.
- analog.scs: analog model
- cosim.conf: A/D configuration
- model.lvl3: MOS model file
- cosim.f.vcs: VCS run arguments
- vcspli.tab: PLI registration table
- runvcsaditq: run script for VCS
runvcsaditq
vcsaditq -CX5345 -full64 -Mupdate +vpi \
-f spmod.f.vcs \
....
-P vcspli.tab
simvaditq | tee cosim.log
spmod.f.vcs
// vlog src
spmod.v
// macros
+define+COSIM
+plusarg_save
+vpi
// config file
+evercad=spmod.conf
// log file
-l spmod.log
Configuration file
/*
* COMMAND ARGUMENT
*/
// adit command = "-sp analog.scs analog.f +showtranstime"
/*
* A/D INTERFACE CHARACTERISTICS
*/
// adit logic_1 = 3.3
// adit logic_0 = 0
// adit rise_time = 500ps
// adit fall_time = 500ps
// adit rounding = 0.5
/*
* A/D CONNECTION SCOPE
*/
// adit auto_connect = 0
// adit top_module = "test"
// adit spice_module = "inva"
Xilinx FPGA
editROM Generation
edit- Generate ROM by .xco in the batch mode
- MIF used for simulation
- COE used for coregen, and after translating .MIF
- Flow should be: .XCO+.MIF -> mif2coe -> execute .NGC/.V -> synthesis
- Files are in SVN: .XCO, .MIF, .V, (.NGC)
.bat
NEWPROJECT "$cgpname"
SET workingdirectory="./tmp"
SET projectname="$romname"
EXECUTE "$romname.xco"
.coe
memory_initialization_radix=2/16;
memory_initialization_vector=
010010110101...