Aneesh Nainani was born in Rajasthan, India. He received the B.Tech and M.Tech degrees in electrical engineering from the Indian Institute of Technology Bombay, Mumbai, India, both in 2007 and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 2011. During his graduate studies, he was an intern at CEA-LETI, IBM Microelectronics, SEMATECH, and Applied Materials, Inc. He is currently a Senior Device Researcher with Applied Materials, Santa Clara, CA, and also holds a Lecturer and Visiting Scholar appointment at Stanford University. He currently serves on the technical working group at International Technology Roadmap for Semiconductors (ITRS) and on the Technical Advisory Board for Device Sciences at Semiconductor Research Corporation (SRC). He has published more than 40 papers on nanocrystal flash memory, III-V CMOS, and thin-film solar cells. His research interests are in the physics and technology of semiconductors devices.
Dr. Nainani was a recipient of several awards, including the Intel PhD Fellowship, the School of Engineering Fellowship from Stanford University, and the National Talent Scholarship from the Government of India
Home Page : https://people.stanford.edu/nainani/
He can be contacted at aneeshnainani[nospam]gmail[dot]com