The Teramac was an experimental massively parallel computer designed by HP in the 1990s. The name reflected the project's vision to provide a programmable gate array system with capacity for a million gates running at a megahertz. Contrary to traditional systems, which are useless if there is one defect, Teramac used defective processors -- intentionally -- to demonstrate its defect-tolerant architecture. Even though the computer had 220,000 hardware defects, it was able to perform some tasks 100 times faster than a single-processor high-end workstation.

Teramac was originally developed by scientists in HP's central research lab, HP Labs, in the mid 1990s. Although it contained conventional silicon integrated circuit technology, it paved the way for some of HP's work in nanoelectronics because it provided an architecture on which a chemically assembled computer could operate.

The experience from this program was used to design the Field Programmable Nanowire Interconnect circuit.

Further readingEdit

  • "A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology (abstract)". Science 12 June 1998: Vol. 280. no. 5370, pp. 1716 - 1721 doi:10.1126/science.280.5370.1716. External link in |publisher= (help)
  • Bruce Culbertson (1998). "Teramac: the million-gate defect-tolerant Custom Computer". HP Laboratories.