Template:AMD Turion II (Champlain, dual-core)

Model number Clock
speed
L2 cache FPU width[1] Hyper
Transport
Multi TDP Socket Release date Part number
Turion II P520 2.3 GHz 2 × 1 MB 128-bit 1.8 GHz 11.5× 25 W Socket S1G4 May 12, 2010 TMP520SGR23GM
Turion II P540 2.4 GHz 2 × 1 MB 128-bit 1.8 GHz 12× 25 W Socket S1G4 October 4, 2010 TMP540SGR23GM
Turion II P560 2.5 GHz 2 × 1 MB 128-bit 1.8 GHz 12.5× 25 W Socket S1G4 October 19, 2010 TMP560SGR23GM
Turion II N530 2.5 GHz 2 × 1 MB 128-bit 1.8 GHz 12.5× 35 W Socket S1G4 May 12, 2010 TMN530DCR23GM
Turion II N550 2.6 GHz 2 × 1 MB 128-bit 1.8 GHz 13× 35 W Socket S1G4 October 4, 2010 TMN550DCR23GM
Turion II N570 2.7 GHz 2 × 1 MB 128-bit 1.8 GHz 13.5× 35 W Socket S1G4 January 4, 2011 TMN570DCR23GM

References

  1. ^ "The 2010 AMD Mainstream Platform". Amd.com. Retrieved 2014-04-30.