Wikipedia

Paul Richman

Paul Richman (born November 17, 1942) is an American semiconductor physicist and author.[1][2]

Paul Richman
Born(1942-11-17)November 17, 1942
New York
NationalityAmerican
EducationMassachusetts Institute of Technology (B.S.)
Columbia University (M.S.)
AwardsElected Fellow of the IEEE
IEEE Harold A. Wheeler Award (1998)
IEEE Third Millennium medal (2000)
Scientific career
FieldsSemiconductor physics
InstitutionsGeneral Telephone and Electronics
Standard Microsystems Corp

Education

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In 1963, Richman studied at M.I.T. and graduated with a Bachelor of Science in electrical engineering. In 1964, he earned a Master of Science in electrical engineering from Columbia University.[3]

Career

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In 1971, Richman co-founded Standard Microsystems Corp (SMSC) as a research and development firm.[4][5] Before co-founding SMSC, he worked as a semiconductor physicist at General Telephone and Electronics.[6] In 1987, he moved to Japan with his family and started a collaboration called Standard Microsystems Japan.[4] Between 1971 and 1999, he served as the chief executive officer, president and chairman of Standard Microsystems.[7][8] During his tenure, SMSC became the largest chip maker on Long Island, and Intel Corp acquired a stake in the company.[4][9] Newsday has called him a pioneer in the computer chip industry.[4] He introduced a method for decreasing the size of chips by moving transistors closer together while increasing operating speeds and as a result devices operate quickly and efficiently.[4]

As an academic, Richman served as a visiting professor of electrical engineering at the City University of New York between 1974 and 1975 and at the State University of New York at Stony Brook between 1975 and 1987.[10]

From 1998 to 2002, he served on the Massachusetts Institute of Technology's Visiting Committee for Electrical Engineering and Computer Science.

Richman developed and held the basic patent for COPLAMOS technology, which pioneered the use of field-doped, locally-oxidized structures in metal–oxide–semiconductor (M.O.S.) integrated circuits.[2][11]

Awards

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  • 1982: Elected a Fellow of the Institute of Electrical and Electronics Engineers, the IEEE.[13]
  • 1998: IEEE's Harold A. Wheeler Award.[13]
  • 2000: IEEE's Third Millennium medal.[14]
  • 2012: Elected to the Long Island Technology Hall of Fame.[15]

Patents

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  • Complementary Enhancement Type MOS Transistors. [16]
  • Method for Manufacturing Metal-Oxide Silicon Devices. [17]
  • Method for Selectively Establishing Regions of Different Surface Charge Densities in a Silicon Wafer. [18]
  • Method of Modifying Electrical Characteristics of MOS Devices Using Ion Implantation.[19]
  • Semiconductor Integrated Circuit Structure with Selectively Modified Insulation Layer.[20]
  • Hermetic plastic dual-in-line package for a semiconductor integrated circuit.[21]
  • Solid State Field Effect Device.[22]
  • Insulated-gate Field Effect Transistors Utilizing a High Resistivity Substrate.[23]
  • MOS Field-effect Transistor Structure with Mesa-like Contact and Gate Areas and Selectively Deeper Junctions.[24]
  • Bipolar MOS Field Effect Transistor.[25]
  • MOS Integrated Circuit with Substrate Containing Selectively Formed Resistivity Regions.[26]
  • Method of Fabricating High Density Refractory Metal Gate MOS Integrated Circuits Utilizing the Gate as a Selective Diffusion and Oxidation Mask.[27]
  • Integrated MOS circuit.[28]
  • Method for Manufacturing a Composite Device, Of the Metal-oxide-semiconductor Type, Control Electrode with Low Superficial Resistivity, And Device Obtained.[29]
  • MOS Integrated Circuit Structure and Method for Its Fabrication.[30]

References

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  1. ^ "SMSC sold to Arizona company for $939M". Newsday.
  2. ^ a b "BUSINESS PEOPLE". The New York Times. July 4, 1979 – via NYTimes.com.
  3. ^ "Alumni of Columbia Engineering — Greater New York City Area". alumnius.net.
  4. ^ a b c d e Bernstein, James (March 30, 2011). "THE SCOOP". Newsday. ProQuest 859030327.
  5. ^ "Leading chip firm stumbles". Crain's. September 19, 2006.
  6. ^ "Selling Technology's Daydreams". The New York Times. ProQuest 120806348.
  7. ^ "SMSC founder retires as CEO".
  8. ^ "Standard Microsystems". WSJ. ProQuest 398106303.
  9. ^ "Intel buys stake in Hauppauge chip maker". ProQuest.
  10. ^ "Richman Steps Down From SMSC".
  11. ^ "News from region 1". IEEE Spectrum. 17 (1): 110. 1980. doi:10.1109/MSPEC.1980.6330239. ISSN 1939-9340.
  12. ^ "1978 Award for Achievement" (PDF). McGraw Hill.
  13. ^ a b "IEEE Long Island Section: 2015 Annual Awards Banquet" (PDF). ieee.li.
  14. ^ "IEEE 2006 Annual Award Ceremony" (PDF). IEEE Long Island. Retrieved October 27, 2022.
  15. ^ "The 2012 LITHF Inductees". stonybrook.
  16. ^ "Complementary Enhancement Type MOS Transistors". USPTO.
  17. ^ "Method for Manufacturing Metal-Oxide Silicon Devices". USPTO.
  18. ^ Method for Selectively Establishing Regions of Different Surface Charge Densities in a Silicon Wafer. USPTO
  19. ^ Method of Modifying Electrical Characteristics of MOS Devices Using Ion Implantation. USPTO
  20. ^ Semiconductor Integrated Circuit Structure with Selectively Modified Insulation Layer. USPTO
  21. ^ Hermetic plastic dual-in-line package for a semiconductor integrated circuit. USPTO
  22. ^ Solid State Field Effect Device. USPTO
  23. ^ Insulated-gate Field Effect Transistors Utilizing a High Resistivity Substrate. USPTO
  24. ^ MOS Field-effect Transistor Structure with Mesa-like Contact and Gate Areas and Selectively Deeper Junctions. USPTO
  25. ^ Bipolar MOS Field Effect Transistor. USPTO
  26. ^ MOS Integrated Circuit with Substrate Containing Selectively Formed Resistivity Regions. USPTO
  27. ^ Method of Fabricating High Density Refractory Metal Gate MOS Integrated Circuits Utilizing the Gate as a Selective Diffusion and Oxidation Mask. USPTO
  28. ^ Integrated MOS circuit. USPTO
  29. ^ Method for Manufacturing a Composite Device, Of the Metal-oxide-semiconductor Type, Control Electrode with Low Superficial Resistivity, And Device Obtained. USPTO
  30. ^ MOS Integrated Circuit Structure and Method for Its Fabrication. Google Patents
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