OR-AND-invert gates or OAI-gates are logic gates comprising OR gates followed by a NAND gate. They can be efficiently implemented in logic families like CMOS and TTL. They are dual to AND-OR-invert gates.

Overview

edit

OR-AND-invert gates implement the inverted product of sums.   groups of  ,   input signals combined with OR, and the results then combined with NAND.

Examples

edit

2-1 OAI-gate

edit
 
Symbol for an 2-1 OAI-gate. The OR gate has the inputs A and B.

A 2-1-OAI gate realizes the function

 

with the truth table shown below.

Truth table 2-1 OAI
Input
A   B   C
Output
Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

2-2 OAI gate

edit

A 2-2-OAI gate realizes the function

 

with the truth table shown below.

Truth table 2-2 OAI
INPUT
A   B   C   D
OUTPUT
Q
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

Realization

edit
 
Implementation of a 3-1 OAI-gate in CMOS

OAI-gates can efficiently be implemented as complex gates. An example of a 3-1 OAI-gate is shown in the figure below.[1]

Examples of use

edit

One possibility of implementing an XOR gate is by using a 2-2-OAI-gate with non-inverted and inverted inputs. [2]

 
Implementation of an XOR gate using a 2-2-OAI gate

References

edit
  1. ^ Hendrichs, Norman. "CMOS OAI31 or-and-invert complex gate". University of Hamburg. Retrieved 2024-02-12.
  2. ^ Fischer, P. "Aussagenlogik und Gatter" (PDF). University of Heidelberg. Retrieved 2024-01-21.