File:31 bit Fibonacci linear feedback shift register.webm

Original file(WebM audio/video file, VP9, length 30 s, 1,920 × 1,080 pixels, 348 kbps overall, file size: 1.25 MB)

Summary

Description
English: A Fibonacci 31 bit linear feedback shift register with taps at positions 28 and 31, giving it a maximum cycle and period at this speed of nearly 6.7 years. The circuit uses 4x74HC565N for the shift registers, a 74HC86N for the XOR and an inverter, and an LMC555 timer for clock pulses.
Date
Source Own work
Author Frussetpouch

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Captions

A 31 bit max cycle Fibonacci linear feedback shift register with taps at 28 and 31

Items portrayed in this file

depicts

19 June 2019

video/webm

55466424a98e3f344ac0f6de3526760bb48d6820

1,305,884 byte

30 second

1,080 pixel

1,920 pixel

File history

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Date/TimeThumbnailDimensionsUserComment
current21:54, 19 June 201930 s, 1,920 × 1,080 (1.25 MB)FrussetpouchUser created page with UploadWizard
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