This article needs additional citations for verification. (September 2015) (Learn how and when to remove this template message)
The 130 nanometer (130 nm) process refers to the level of MOSFET (CMOS) semiconductor process technology that was commercialized around the 2001-2002 timeframe, by leading semiconductor companies like Fujitsu, IBM, Intel, Texas Instruments, and TSMC.
The origin of the 130 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).
Their first MOSFET demonstrated by Egyptian engineer Mohamed Atalla and Korean engineer Dawon Kahng in 1960 had a gate length of 20 µm and a gate oxide thickness of 100 nm. In 1984, a MOSFET based on NMOS logic was fabricated with a 100 nm channel length by Toshio Kobayashi, Seiji Horiguchi and K. Kiuchi at Nippon Telegraph and Telephone (NTT) in Japan.
In 1990, a 100 nm CMOS process was demonstrated by an IBM T.J. Watson Research Center team led by Iranian engineers Ghavam G. Shahidi and Bijan Davari and Taiwanese engineer Yuan Taur. In 2001, 100 nm CMOS nodes were commercialized by Fujitsu and IBM.
Processors using 130 nm manufacturing technologyEdit
- Fujitsu SPARC64 V - 2001
- Gekko by IBM and Nintendo (GameCube console) - 2001
- Motorola PowerPC 7447 and 7457 - 2002
- IBM PowerPC G5 970 - October 2002 - June 2003
- Intel Pentium III Tualatin - 2001-04
- Intel Celeron Tualatin-256 - 2001-10-02
- Intel Pentium M Banias - 2003-03-12
- Intel Pentium 4 Northwood- 2002-01-07
- Intel Celeron Northwood-128 - 2002-09-18
- Intel Xeon Prestonia and Gallatin - 2002-02-25
- VIA C3 - 2001
- AMD Athlon XP Thoroughbred, Thorton, and Barton
- AMD Athlon MP Thoroughbred - 2002-08-27
- AMD Athlon XP-M Thoroughbred, Barton, and Dublin
- AMD Duron Applebred - 2003-08-21
- AMD K7 Sempron Thoroughbred-B, Thorton, and Barton - 2004-07-28
- AMD K8 Sempron Paris - 2004-07-28
- AMD Athlon 64 Clawhammer and Newcastle - 2003-09-23
- AMD Opteron Sledgehammer - 2003-06-30
- Elbrus 2000 1891ВМ4Я (1891VM4YA) - 2008-04-27 
- MCST-R500S 1891BM3 - 2008-07-27 
- Vortex 86SX - 
- 65nm CMOS Process Technology
- Sze, Simon M. (2002). Semiconductor Devices: Physics and Technology (2nd ed.). Wiley. p. 4. ISBN 0-471-33372-7.
- Kobayashi, Toshio; Horiguchi, Seiji; Kiuchi, K. (December 1984). "Deep-submicron MOSFET characteristics with 5 nm gate oxide". 1984 International Electron Devices Meeting: 414–417. doi:10.1109/IEDM.1984.190738.
- Shahidi, Ghavam G.; Davari, Bijan; Taur, Yuan; Warnock, James D.; Wordeman, Matthew R.; McFarland, P. A.; Mader, S. R.; Rodriguez, M. D. (December 1990). "Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing". International Technical Digest on Electron Devices: 587–590. doi:10.1109/IEDM.1990.237130.
- Krewell, Kevin (21 October 2002). "Fujitsu's SPARC64 V Is Real Deal". Microprocessor Report.
- Микропроцессор Эльбрус/МЦСТ. Mcst.ru (in Russian). Retrieved 2015-09-10.
- "Микропроцессор МЦСТ R500S/МЦСТ". Mcst.ru (in Russian). Archived from the original on 2015-11-01. Retrieved 2015-09-10.
- "CPU from DM&P". Dmp.com.tw. Retrieved 2015-09-10.
|MOSFET manufacturing processes||Succeeded by|
|This nanotechnology-related article is a stub. You can help Wikipedia by expanding it.|