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The 90 nanometer (90 nm) process refers to the level of CMOS process technology that was reached in the 2004–2005 timeframe, by most leading semiconductor companies, like Intel, AMD, Infineon, Texas Instruments, IBM, and TSMC.

The origin of the 90 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).

The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.

Even more significantly, the 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.


Example: Elpida 90 nm DDR2 SDRAM process[1]Edit

  • Use of 300 mm wafer size
  • Use of KrF (248 nm) lithography with optical proximity correction
  • 512 Mbit
  • 1.8 V operation
  • Derivative of earlier 110 nm and 100 nm processes

Processors using 90 nm process technologyEdit

See alsoEdit


  1. ^ Elpida's presentation at Via Technology Forum 2005 and Elpida 2005 Annual Report

External linksEdit

Preceded by
130 nm
CMOS manufacturing processes Succeeded by
65 nm