Quasi-delay-insensitive circuit(Redirected from Quasi-delay-insensitive)
In digital logic design, quasi delay-insensitive (QDI) or speed independent (SI) circuits are the most robust class of asynchronous circuit that are still turing-complete. While delay-insensitive circuits make no assumptions regarding the delay of wires or gates and are not Turing-complete[timing 1], QDI circuits make the weakest delay assumption necessary to be so, the isochronic fork[timing 2].
- QDI circuits will operate correctly regardless of timing variations produced by process variation, temperature fluctuation, circuit redesign, and FPGA remapping as long as the isochronic fork assumption is not violated.
- Control circuitry requiring complex event sequencing comes naturally in QDI circuits.
- Idle devices do not switch and QDI processes have a cycle time dependent upon the computation. This gives designers the opportunity to save dynamic power and increase throughput by optimizing for average-case workload characteristics instead of worst-case.
- Data encoding is extremely sparse, typically requiring twice as many wires.
- QDI circuits require many more devices than synchronous circuits to implement the same functionality.
- The baseline QDI pipeline is slower and more power hungry than the baseline synchronous pipeline.
QDI circuits have been used to manufacture a large number of research chips, a small selection of which follows.
A QDI circuit is a system of events which are organized as a network of interacting cycles. In this system, a gate is mapped to two events in which its output node is driven either from GND to Vdd by the pull up network or from Vdd to GND by the pull down network. Furthermore, these two events must belong to the same cycles and every cycle must have an odd number of gates. The simplest example, a ring oscillator, consists of exactly one cycle of three gates (six events).
Two cycles may interact using a c-element which waits for its inputs to match before copying the value to its output. This effectively forces the two cycles to synchronize at the c-element. Connecting three or more of these cycles in a line creates a pipeline allowing the cycles to trigger one after another like dominoes.
This representation makes it relatively easy to understand small systems, but quickly becomes too much to manage as systems get larger. So, larger systems are partitioned into modules called processes which describe the interaction between a set of cycles. A process boundary cuts all of the participating cycles which then act as channel ports each with two circuit nodes called the request and acknowledge. The process that drives the request is the sender while the process that drives the acknowledgement is the receiver. Now, the sender and receiver communicate using certain protocols[synthesis 1] and the sequential triggering of communication actions from one process to the next is referred to as a token that traverses the pipeline.
Stability and non-interferenceEdit
The correct operation of a QDI circuit requires that events be limited to monotonic digital transitions. Instability (glitch) or interference (short) can force the system into illegal states causing incorrect/unstable results, deadlock, and circuit damage. The previously described cyclic structure that ensures stability is called acknowledgement. A transition
T1 is acknowledges another
T2 if there is a causal sequence of events from
T2 that prevents
T2 from occurring until
T1 has completed.[timing 3][timing 4][timing 1] In a QDI circuit, every transition must acknowledge every one of the inputs to its associated gate. However, there are a few exceptions in which the stability property maintained using timing assumptions guaranteed with layout constraints[layout 1] rather than causality.
Isochronic fork assumptionEdit
An isochronic fork is a wire fork in which one end does not acknowledge the transition driving the wire. A good example of such a fork can be found in the standard implementation of a pre-charge half buffer. There are two types of Isochronic forks. An asymmetric isochronic fork assumes that the transition on the non-acknowledging end happens before or when the transition has been observed on the acknowledging end. A symmetric isochronic fork ensures that both ends observe the transition simultaneously. In QDI circuits, every transition that drives a wire fork must be acknowledged by at least one end of that fork. This concept was first introduced by A. J. Martin to distinguish between asynchronous circuits that satisfy QDI requirements and those that do not. Martin also established that it is impossible to design useful systems without including at least some isochronic forks given reasonable assumptions about the available circuit elements.[timing 1] Isochronic forks were long thought to be the weakest compromise away from fully delay-insensitive systems.
In fact, every CMOS gate has one or more internal isochronic forks between the pull-up and pull-down networks. The pull-down network only acknowledges the up-going transitions of the inputs while the pull-up network only acknowledges the down-going transitions.
Adversarial path assumptionEdit
The adversarial path assumption also deals with wire forks, but is ultimately weaker than the isochronic fork assumption. At some point in the circuit after a wire fork, the two paths must merge back into one. The adversarial path is the one that fails to acknowledge the transition on the wire fork. This assumption states that the transition propagating down the acknowledging path reaches the merge point after it would have down the adversarial path.[timing 4] This effectively extends the isochronic fork assumption beyond the confines of the forked wire and into the connected paths of gates.
Half-cycle timing assumptionEdit
This assumption relaxes the QDI requirements a little further in the quest for performance. The c-element is effectively three gates, the logic, the driver, and the feedback and is non-inverting. This gets to be cumbersome and expensive if there is a need for a large amount of logic. The acknowledgement theorem states that the driver must acknowledge the logic. The half-cycle timing assumption assumes that the driver and feedback will stabilize before the inputs to the logic are allowed to switch.[timing 5] This allows the designer use the output of the logic directly, bypassing the driver and making shorter cycles for higher frequency processing.
Atomic complex gatesEdit
A large amount of the automatic synthesis literature uses atomic complex gates. A tree of gates is assumed to transition completely before any of the inputs at the leaves of the tree are allowed to switch again.[timing 6][timing 7] While this assumption allows automatic synthesis tools to bypass the bubble reshuffling problem, the reliability of these gates tends to be difficult to guarantee.
Relative Timing is a framework for making and implementing arbitrary timing assumptions in QDI circuits. It represents a timing assumption as a virtual causality arc to complete a broken cycle in the event graph. This allows designers to reason about timing assumptions as a method to realize circuits with higher throughput and energy efficiency by systematically sacrificing robustness.[timing 8][timing 9]
Communicating hardware processes (CHP)Edit
Communicating hardware processes (CHP) is a program notation for QDI circuits inspired by Tony Hoare's communicating sequential processes (CSP) and Edsger W. Dijkstra's guarded commands. The syntax is described below in descending precedence.[synthesis 2]
skipdoes nothing. It simply acts as a placeholder for pass-through conditions.
- Dataless assignment
a+sets the voltage of the node
ato Vdd while
a-sets the voltage of
a := eevaluates the expression
ethen assigns the resulting value to the variable
X!eevaluates the expression
ethen sends the resulting value across the channel
X!is a dataless send.
X?awaits until there is a valid value on the channel
Xthen assigns that value to the variable
X?is a dataless receive.
#Xreturns the value waiting on the channel
Xwithout executing the receive.
- Simultaneous composition
S * Texecutes the process fragments
Tat the same time.
- Internal parallel composition
S, Texecutes the process fragments
Tin any order.
- Sequential composition
S; Texecutes the process fragments
- Parallel composition
S || Texecutes the process fragments
Tin any order. This is functionally equivalent to internal parallel composition but with lower precedence.
- Deterministic selection
[G0 -> S0G1 -> S1...Gn -> Sn]implements choice in which
G0,G1,...,Gnare guards which are dataless boolean expressions or data expressions that are implicitly cast using a validity check and
S0,S1,...,Snare process fragments. Deterministic selection waits until one of the guards evaluates to Vdd, then proceeds to execute the guard's associated process fragment. If two guards evaluate to Vdd during the same window of time, an error occurs.
[G]is shorthand for
[G -> skip]and simply implements a wait.
- Non-deterministic selection
[G0 -> S0:G1 -> S1:...:Gn -> Sn]is the same as deterministic selection except that more than one guard is allowed to evaluate to Vdd. Only the process fragment associated with the first guard to evaluate to Vdd is executed.
*[G0 -> S0G1 -> S1...Gn -> Sn]or
*[G0 -> S0:G1 -> S1:...:Gn -> Sn]is similar to the associated selection statements except that the action is repeated while any guard evaluates to Vdd.
*[S]is shorthand for
*[Vdd -> S]and implements infinite repetition.
Hand-shaking expansions (HSE)Edit
Hand-shaking expansions are a subset of CHP in which only dataless operators are permitted. This is an intermediate representation toward the synthesis of QDI circuits.
Petri nets (PN)Edit
A petri net (PN) is a bipartite graph of places and transitions used as a model for QDI circuits. Transitions in the petri net represent voltage transitions on nodes in the circuit. Places represent the partial states between transitions. A token inside a place acts as a program counter identifying the current state of the system and multiple tokens may exist in a petri net simultaneously. However, for QDI circuits multiple tokens in the same place is an error.
When a transition has tokens on every input place, that transition is enabled. When the transition fires, the tokens are removed from the input places and new tokens are created on all of the output places. This means that a transition that has multiple output places is a parallel split and a transition with multiple input places is a parallel merge. If a place has multiple output transitions, then any one of those transitions could fire. However, doing so would remove the token from the place and prevent any other transition from firing. This effectively implements choice. Therefore, a place with multiple output transitions is a conditional split and a place with multiple input transitions is a conditional merge.
Event-rule systems (ER)Edit
Event-rule systems (ER) use a similar notation to implement a restricted subset of petri net functionality in which there are transitions and arcs, but no places. This means that the baseline ER system lacks choice as implemented by conditional splits and merges in a petri net and disjunction implemented by conditional merges. The baseline ER system also doesn't allow feedback, So, it effectively represents a trace of the transitions that fired during the execution of a QDI circuit and is typically used to for timing and sizing optimizations.[sizing 1]
Production rule set (PRS)Edit
A production rule specifies either the pull-up or pull-down network of a gate in a QDI circuit and follows the syntax
G -> S in which
G is a guard as described above and
S is one or more dataless assignments in parallel as described above. In states not covered by the guards, it is assumed that the assigned nodes remain at their previous states. This can be achieved using a staticizor of either weak or combinational feedback (shown in red). The most basic example is the C-element in which the guards do not cover the states where
B are not the same value.
There are many techniques for constructing a QDI circuits, but they can generally be classified into two strategies.
Formal synthesis was introduced by Alain Martin in 1991.[synthesis 2] The method involves making successive program transformations which are proven to maintain program correctness. The goal of these transformations is to convert the original sequential program into a parallel set of communicating process which each map well to a single pipeline stage. The possible transformations include:
- Projection splits a process which has disparate, non-interacting sets of variables into a separate process per set. [synthesis 3]
- Process decomposition splits a process with minimally interacting variables sets into a separate process per set in which each process communicates to another only as necessary across channels.
- Slack matching involves adding pipeline stages between two communicating processes in order to increase overall throughput. [synthesis 4]
Once the program is decomposed into a set of small communicating processes, it is expanded into hand-shaking expansions (HSE). Channel actions are expanded into their constituent protocols and multi-bit operators are expanded into their circuit implementations. These HSE are then reshuffled to optimize the circuit implementation by reducing the number of dependencies.[synthesis 5] Once the reshuffling is decided upon, state variables are added to disambiguate circuit states for a complete state encoding.[synthesis 6] Next, minimal guards are derived for each signal assignment, producing production rules. There are multiple methods for doing this including guard strengthening, guard weakening, and others.[synthesis 2] The production rules are not necessarily CMOS implementable at this point, so bubble reshuffling moves signal inversions around the circuit in an attempt to make it so. However, bubble reshuffling is not guaranteed to succeed. This is where atomic complex gates are generally used in automated synthesis programs.
Syntax directed translationEdit
The second strategy, syntax directed translation, was first introduced in 1988 by Steven Burns and seeks a simpler approach at the expense of circuit performance by mapping each CHP syntax to a hand-compiled circuit.[synthesis 7] Synthesizing a QDI circuit using this method strictly implements the control flow as dictated by the program.
A hybrid approach introduced by Andrew Lines in 1998 transforms the sequential specification into parallel specifications as in formal synthesis, but then uses predefined pipeline templates to implement those parallel processes similar to syntax-directed translation.[synthesis 8] Andrew outlined three efficient logic families or reshufflings.
Weak condition half buffer (PCHB)Edit
Weak condition half buffer (WCHB) is the simplest and fastest of the logic families with a 10 transition pipeline cycle (or 6 using the half-cycle timing assumption). However, it is also limited to simpler computations because more complex computations tend to necessitate long chains of transistors in the pull-up network of the forward driver. More complex computations can generally be broken up into simpler stages or handled directly with one of the pre-charge families. The WCHB is a half buffer meaning that a pipeline of
N stages can contain at most
N/2 tokens at once. This is because the reset of the output request
Rr must wait until after the reset of the input
Pre-charge half buffer (PCHB)Edit
Pre-charge half buffer (PCHB) uses domino logic to implement a more complex computational pipeline stage. This removes the long pull-up network problem, but also introduces an isochronic fork on the input data which must be resolved later in the cycle. This causes the pipeline cycle to be 14 transitions long (or 10 using the half-cycle timing assumption).
Pre-charge full buffer (PCFB)Edit
Pre-charge full buffers (PCFB) are very similar to PCHB, but adjust the reset phase of the reshuffling to implement full buffering. This means that a pipeline of
N PCFB stages can contain at most
N tokens at once. This is because the reset of the output request
Rr is allowed to happen before the reset of the input
Along with the normal verification techniques of testing, coverage, etc, QDI circuits may be verified formally by inverting the formal synthesis procedure to derive a CHP specification from the circuit. This CHP specification can then be compared against the original to prove correctness. [verification 1][verification 2]
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