Transactional Synchronization Extensions(Redirected from Hardware Lock Elision)
Transactional Synchronization Extensions (TSX) is an extension to the x86 instruction set architecture (ISA) that adds hardware transactional memory support, speeding up execution of multi-threaded software through lock elision. According to different benchmarks, TSX can provide around 40% faster applications execution in specific workloads, and 4–5 times more database transactions per second (TPS).
TSX was documented by Intel in February 2012, and debuted in June 2013 on selected Intel microprocessors based on the Haswell microarchitecture. Haswell processors below 45xx as well as R-series and K-series (with unlocked multiplier) SKUs do not support TSX. In August 2014, Intel announced a bug in the TSX implementation on current steppings of Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX feature on affected CPUs via a microcode update.
TSX provides two software interfaces for designating code regions for transactional execution. Hardware Lock Elision (HLE) is an instruction prefix-based interface designed to be backward compatible with processors without TSX support. Restricted Transactional Memory (RTM) is a new instruction set interface that provides greater flexibility for programmers.
TSX enables optimistic execution of transactional code regions. The hardware monitors multiple threads for conflicting memory accesses, while aborting and rolling back transactions that cannot be successfully completed. Mechanisms are provided for software to detect and handle failed transactions.
In other words, lock elision through transactional execution uses memory transactions as a fast path where possible, while the slow (fallback) path is still a normal lock.
Hardware Lock ElisionEdit
Hardware Lock Elision (HLE) adds two new instruction prefixes,
XRELEASE. These two prefixes reuse the opcodes of the existing
REPE prefixes (
F3H). On processors that do not support TSX,
REPE prefixes are ignored on instructions for which the
XRELEASE are valid, thus enabling backward compatibility.
XACQUIRE prefix hint can only be used with the following instructions with an explicit
XCHG instruction can be used without the
LOCK prefix as well.
XRELEASE prefix hint can be used both with the instructions listed above, and with the
MOV mem, reg and
MOV mem, imm instructions.
HLE allows optimistic execution of a critical section by eliding the write to a lock, so that the lock appears to be free to other threads. A failed transaction results in execution restarting from the
XACQUIRE-prefixed instruction, but treating the instruction as if the
XACQUIRE prefix were not present.
Restricted Transactional MemoryEdit
Restricted Transactional Memory (RTM) is an alternative implementation to HLE which gives the programmer the flexibility to specify a fallback code path that is executed when a transaction cannot be successfully executed.
RTM adds three new instructions:
XEND instructions mark the start and the end of a transactional code region; the
XABORT instruction explicitly aborts a transaction. Transaction failure redirects the processor to the fallback code path specified by the
XBEGIN instruction, with the abort status returned in the
|0||Set if abort caused by
|1||If set, the transaction may succeed on a retry. This bit is always clear if bit 0 is set.|
|2||Set if another logical processor conflicted with a memory address that was part of the transaction that aborted.|
|3||Set if an internal buffer overflowed.|
|4||Set if debug breakpoint was hit.|
|5||Set if an abort occurred during execution of a nested transaction.|
TSX provides a new
XTEST instruction that returns whether the processor is executing a transactional region.
||This section needs to be updated. (June 2017)|
Intel's TSX specification describes how the transactional memory is exposed to programmers, but withholds details on the actual transactional memory implementation. Intel specifies in its developer's and optimization manuals that Haswell maintains both read-sets and write-sets at the granularity of a cache line, tracking addresses in the L1 data cache of the processor. Intel also states that data conflicts are detected through the cache coherence protocol.
Haswell's L1 data cache has an associativity of eight. This means that in this implementation, a transactional execution that writes to nine distinct locations mapping to the same cache set will abort. However, due to micro-architectural implementations, this does not mean that fewer accesses to the same set are guaranteed to never abort. Additionally, in CPU configurations with Hyper-Threading Technology, the L1 cache is shared between the two threads on the same core, so operations in a sibling logical processor of the same core can cause evictions.
Independent research points into Haswell’s transactional memory most likely being a deferred update system using the per-core caches for transactional data and register checkpoints. In other words, Haswell is more likely to use the cache-based transactional memory system, as it is a much less risky implementation choice. On the other hand, Intel's Skylake or later may combine this cache-based approach with memory ordering buffer (MOB) for the same purpose, possibly also providing multi-versioned transactional memory that is more amenable to speculative multithreading.
In August 2014, Intel announced that a bug exists in the TSX implementation on Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX feature on affected CPUs via a microcode update. The bug was fixed in F-0 steppings of the vPro-enabled Core M-5Y70 Broadwell CPU in November 2014.
- Richard M. Yoo; Christopher J. Hughes; Konrad Lai; Ravi Rajwar (November 2013). "Performance Evaluation of Intel Transactional Synchronization Extensions for High-Performance Computing" (PDF). intel-research.net. Retrieved 2013-11-14.
- Tomas Karnagel; Roman Dementiev; Ravi Rajwar; Konrad Lai; Thomas Legler; Benjamin Schlegel; Wolfgang Lehner (February 2014). "Improving In-Memory Database Index Performance with Intel Transactional Synchronization Extensions" (PDF). software.intel.com. Retrieved 2014-03-03.
- "Performance Evaluation of Intel Transactional Synchronization Extensions for High Performance Computing". supercomputing.org. November 2013. Retrieved 2013-11-14.
- "Benchmarks: Haswell's TSX and Memory Transaction Throughput (HLE and RTM)". sisoftware.co.uk. Retrieved 2013-11-14.
- "Transactional Synchronization in Haswell". Software.intel.com. Retrieved 2012-02-07.
- "Transactional memory going mainstream with Intel Haswell". Ars Technica. 2012-02-08. Retrieved 2012-02-09.
- "The Core i7-4770K Review". Tom's Hardware. 2013-06-01. Retrieved 2012-06-03.
- "Intel Comparison Table of Haswell Pentium, i3, i5, and i7 models". intel.com. Retrieved 2014-02-11.
- Scott Wasson (2014-08-12). "Errata prompts Intel to disable TSX in Haswell, early Broadwell CPUs". techreport.com. Retrieved 2014-08-12.
- "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium Processor Family, and Desktop Intel Celeron Processor Family: Specification Update (Revision 014)" (PDF). Intel. June 2014. p. 46. Retrieved 2014-08-13.
Under a complex set of internal timing conditions and system events, software using the Intel TSX (Transactional Synchronization Extensions) instructions may observe unpredictable system behavior.
- Wooyoung Kim (2013-07-25). "Fun with Intel Transactional Synchronization Extensions". Intel. Retrieved 2013-11-12.
- Sebastien Dabdoub; Stephen Tu. "Supporting Intel Transactional Synchronization Extensions in QEMU" (PDF). mit.edu. Retrieved 2013-11-12.
- Johan De Gelas (2012-09-20). "Making Sense of the Intel Haswell Transactional Synchronization eXtensions". AnandTech. Retrieved 2013-10-20.
- "Hardware Lock Elision Overview". intel.com. Archived from the original on 2013-10-29. Retrieved 2013-10-27.
- David Kanter (2012-08-21). "Analysis of Haswell's Transactional Memory". Real World Technologies. Retrieved 2013-11-19.
- "Intel 64 and IA-32 Architectures Software Developer’s Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, and 3C" (PDF). Intel. September 2013. p. 342. Retrieved 2013-11-19.
- "Intel 64 and IA-32 Architectures Optimization Reference Manual" (PDF). Intel. September 2013. p. 446. Retrieved 2013-11-19.
- "Intel TSX implementation properties". Intel. 2013. Retrieved 2013-11-14.
The processor tracks both the read-set addresses and the write-set addresses in the first level data cache (L1 cache) of the processor.
- De Gelas, Johan (September 20, 2012). "Making Sense of the Intel Haswell Transactional Synchronization eXtensions". AnandTech. Retrieved 23 December 2013.
The whole "CPU does the fine grained locks" is based upon tagging the L1 (64 B) cachelines and there are 512 of them to be specific (64 x 512 = 32 KB). There is only one "lock tag" per cacheline.
- David Kanter (2012-08-21). "Haswell Transactional Memory Alternatives". Real World Technologies. Retrieved 2013-11-14.
- Ian Cutress (2014-08-12). "Intel Disables TSX Instructions: Erratum Found in Haswell, Haswell-E/EP, Broadwell-Y". AnandTech. Retrieved 2014-08-30.
- "Intel Core M Processor Family. Specification Update. December 2014. Revision 003. 330836-003" (PDF). Intel. December 2014. p. 10. Retrieved 2014-12-28.
BDM53 1 E-0: X, F-0:, Status: Fixed ERRATA: Intel TSX Instructions Not Available. 1. Applies to Intel Core M-5Y70 processor. Intel TSX is supported on Intel Core M-5Y70 processor with Intel vPro Technology. Intel TSX is not supported on other processor SKUs.line feed character in
|quote=at position 190 (help)
- Presentation from IDF 2012 (PDF)
- Adding lock elision to Linux, Linux Plumbers Conference 2012 (PDF)
- Lock elision in the GNU C library, LWN.net, January 30, 2013, by Andi Kleen
- TSX Optimization Guide, Chapter 12 (PDF)
- Web Resources about Intel Transactional Synchronization Extensions
- x86, microcode: BUG: microcode update that changes x86_capability, LKML, September 2014 (there is also another similar bug report)
- Intel microcode, Gentoo, September 19, 2015