This diagram is incorrect. The transition from I to E should be BusRd(!S)[1]. Furthermore, there is a distinction between Flush and Flush' where the later serves the request directly from the processors cache. Sam Pattuzzi (talk) 12:30, 4 November 2013 (UTC)
References edit
- ^ David E. Culler, Jaswinder Pal Singh, Anoop Gupta (1999). Parallel Computer Architecture: A Hardware/software Approach ([Nachdr.] ed.). Gulf Professional Publishing. p. 301. ISBN 1558603433.
{{cite book}}: CS1 maint: multiple names: authors list (link)
