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Summary
| Description |
English: Niagara 3 / UltraSPARC T3 / OpenSPARC T3 - chip floorplan |
| Date | February 13, 2010 |
| Source | I (DavidHalko) hand-drew this work from ISSCC 2010 public marketing presentation from Sun Microsystems referenced from arstechnica.com. |
| Author | David Halko |
| Other versions | http://static.arstechnica.com/uptime/niagara-3.png |
Licensing
I, the copyright holder of this work, hereby publish it under the following license:
This file is licensed under the Creative Commons Attribution 3.0 Unported license.
- You are free:
- to share – to copy, distribute and transmit the work
- to remix – to adapt the work
- Under the following conditions:
- attribution – You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
File history
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 21:44, 13 February 2010 | | 508 × 532 (19 KB) | DavidHalko | {{Information |Description = Niagra 3 / UltraSPARC T3 / OpenSPARC T3 - Die Micrograph |Source = I (DavidHalko) created this work entirely by myself. |Date = February 13, 2010 |Author = David Halko |other_versions = }} |
File usage
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