Hey y'all:

I am not sure how the timing diagram figure gets generated, so I can't really help in editing it. The SI and SO data lines for both phase A and Phase B need to have the inputs and outputs shifted by 1/2 clock cycle from each other. Thanks. Other than that a very well written page. 165.225.38.148 (talk) 17:07, 1 April 2020 (UTC) Ray MackReply