The Open Verification Methodology (OVM) is a documented methodology with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008,[1] and regular updates have expanded its functionality. The latest version is OVM 2.1.2, released in January, 2011.
The reuse concepts within the OVM were derived mainly from the Universal Reuse Methodology (URM) which was, to a large part, based on the e Reuse Methodology (ERM) for the e Verification Language developed by Verisity Design in 2001. The OVM also brings in concepts from the Advanced Verification Methodology (AVM). The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare, etc.). The UVM also has recommendations for code packaging and naming conventions.
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External links edit
- EDA Playground - run OVM simulations from a web browser (free online IDE)
- OVM Relationship to the UVM