||This article needs additional citations for verification. (April 2013)|
The term derives from the fact that in domino logic (cascade structure consisting of several stages), each stage ripples the next stage for evaluation, similar to a Domino falling one after the other.
Dynamic Logic Drawbacks
In Dynamic logic, problem arises when cascading one gate to the next. The precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the "precharge" of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error.
In order to cascade dynamic logic gates, one solution is Domino Logic, which inserts an ordinary static inverter between stages. While this might seem to defeat the point of dynamic logic, since the inverter has a pFET (one of the main goals of Dynamic Logic is to avoid pFETs where possible, due to speed), there are two reasons it works well. First, there is no fanout to multiple pFETs. The dynamic gate connects to exactly one inverter, so the gate is still very fast. And since the inverter connects to only nFETs in dynamic logic gates, it too is very fast. Second, the pFET in an inverter can be made smaller than in some types of logic gates.
In Domino logic cascade structure of several stages, the evaluation of each stage ripples the next stage evaluation, similar to a domino falling one after the other. Once fallen, the node states cannot return to "1" (until the next clock cycle) just as dominos, once fallen, cannot stand up, justifying the name Domino CMOS Logic. It contrasts with other solutions to the cascade problem in which cascading is interrupted by clocks or other means.
- They have smaller areas than conventional CMOS logic (as does all Dynamic Logic).
- Parasitic capacitances are smaller so that higher operating speeds are possible.
- Operation is free of glitches as each gate can make only one transition.
- Only non-inverting structures are possible because of the presence of inverting buffer.
- Charge distribution may be a problem.
- * Knepper. "SC571 VLSI Design Principles," Chapter 5: "Dynamic Logic Circuits"
- Abdel-Hafeez and Ranjan. "Single Rail Domino Logic For Four-Phase Clocking Scheme"
- Chung-Yu Wu; Kuo-Hsing Cheng; Jinn-Shyan Wan. "Analysis and design of a new race-free four-phase CMOS logic", Solid-State Circuits, IEEE Journal of Volume 28, Issue 1, Jan 1993 Page(s):18 - 25
Read in another language
This page is available in 1 language