Amiga Chip RAM
Chip RAM is a commonly used term for the integrated RAM used in Commodore's line of Amiga computers. Chip RAM is shared between the central processing unit (CPU) and the Amiga's dedicated chipset (hence the name). It was also, rather misleadingly, known as "graphics RAM".
Direct memory access
Under the Amiga architecture, the Agnus (Alice on AGA models) coprocessor is the direct memory access (DMA) controller. Both the CPU and other members of the chipset have to arbitrate for access to shared RAM via Agnus. This allows the custom chips to perform video, audio or other DMA operations independently of the CPU. As the 68000 processor used in early Amiga systems usually accesses memory on every second memory cycle, Agnus operates a system where the "odd" clock cycle is allocated to time-critical custom chip access and the "even" cycle is allocated to the CPU, thus the CPU is not typically blocked from memory access and may run without interruption. However, certain chipset DMA, such as copper or blitter operations, can use any spare cycles, effectively blocking cycles from the CPU. In such situations CPU cycles are only blocked while accessing shared RAM, but never when accessing external RAM or ROM.
Chip RAM by model
Most stock Amiga systems were equipped with chip RAM only and shipped with between 256 kB and 2 MB.
|Model||Stock chip RAM||Maximum chip RAM||Width|
|Amiga 1000||256 kiB||512 kiB||16-bit|
|Amiga 500, Amiga 2000, CDTV||512 kiB - 1 MiB[a]||512 kiB - 1 MiB[b]||16-bit|
|Amiga 500 Plus, Amiga 600||1 MiB||2 MiB||16-bit|
|Amiga 3000||1 MiB||2 MiB||32-bit[c]|
|Amiga 1200, Amiga 4000, Amiga CD32||2 MiB||2 MiB||32-bit|
The shared RAM data bus is 16-bit on OCS and ECS systems[c]. The later AGA systems use a 32-bit data bus controlled by the Alice coprocessor (replacing Agnus) and 32-bit RAM. The memory clock runs at double the rate on AGA systems. As a result, chipset RAM bandwidth is increased fourfold compared to the earlier 16-bit design. The ECS-based A3000 also has 32-bit shared RAM but access is only 32 bit for CPU operations; the chipset remained 16-bit.
The maximum amount of chip RAM is dependent on the Agnus/Alice version. The original Agnus chip fitted to the A1000 and early A2000 systems is a 48-pin DIP package able to address 512 kiB of chip RAM. Subsequent versions of the Agnus are in an 84-pin PLCC package (either socketed or surface-mounted). All models, except the A1000, are upgradable to 2 MiB of chip RAM. The A500, and later versions of the A2000, with hardware modification can accommodate 1 MiB by installing a later revision Agnus chip (8732A); late-production machines usually already contained that chip, so that only jumper modifications were necessary. Likewise, 2 MB can be installed by fitting an 8372B Agnus and extra memory.
The maximum amount of chip RAM in any model is 2 MiB. The Amiga 4000 motherboard includes a non-functional jumper that claims to accommodate 8 MiB of chip RAM - regardless of its position, the system only recognizes 2 MiB due to the limitations of the Alice chip. However, the software emulator, UAE, can emulate an Amiga system with up to 8 MiB of chip RAM.
Amiga systems can also be expanded with, so called, "fast" RAM, which is only accessible to the CPU. This improves execution speed as CPU cycles are never blocked even when the custom chipset is simultaneously accessing chip RAM. Adding "fast" RAM to systems with 32-bit CPUs approximately doubles the instruction speed.
Confusingly, a system may have several different kinds and speeds of fast RAM. For example, an Amiga 3000 may contain 16-bit Zorro II expansion RAM, 32-bit Zorro III expansion RAM, 32-bit motherboard RAM and 32-bit CPU card RAM simultaneously (in increasing speed order). Automatically configured RAM is prioritized by the system, so the fastest memory is used first.
Early versions of the Amiga 2000B, and the most common "trapdoor memory expanded" configuration of the Amiga 500, contain 512 KB pseudo fast RAM ("slow RAM") controlled by Agnus with the same limitations as chip RAM, yet unusable as such due to register limitations. Numerous budget trapdoor expansions for the 500 extended this 'controllerless' concept to up to 1.8 MB 'slow' RAM (requiring a Gary adapter for addressing).