The Z8000 ("zee- or zed-eight-thousand") is a 16-bit microprocessor introduced by Zilog in early 1979. The architecture was designed by Bernard Peuto while the logic and physical implementation was done by Masatoshi Shima, assisted by a small group of people. In contrast to most designs of the era, the Z8000 did not use microcode which allowed it to be implemented in only 17,500 transistors.
|16× 16-bit general purpose|
Z8001 on the motherboard of an Olivetti M20 computer
|Data width||16 bits|
|Address width||23 bits|
The Z8000 was not Z80-compatible, although it featured many of the well-received design notes that made the Z80 popular. Among these was the ability for its registers to be combined together and used as a single larger register - while the Z80 allowed two 8-bit registers to be used as a single 16-bit register, the Z8000 expanded this by allowing two 16-bit registers to operate as a 32-bit register, or four to operate as a 64-bit register. These combined registers were particularly useful for mathematical operations.
Although it was an attractive design for its era, and saw some use in the early 1980s, it was never as popular as the Z80. Federico Faggin, then CEO of Zilog, believes a reason for this was that Zilog was mainly owned by a single investor, Exxon Enterprises, which had ambitions to compete with IBM. Thus, when IBM began the IBM PC project, they saw Zilog as a competitor, and chose the Intel 8088 over the Z8000 as Intel was not seen as competition in the computer market. But the Z8000's launch date placed it between the Intel 8086 (April 1978), and the Motorola 68000 (September 1979), the latter of which had a 32-bit instruction set architecture and was roughly twice as fast.
The Zilog Z80000 was a 32-bit follow-on design, launched in 1986.
|The Z8000 registers|
|0||Segment||0 0 0 0 0 0 0 0||Program Counter|
The Z8000 initially shipped in two versions; the Z8001 with a full 24-bit external address bus to allow it to access up to 8 megabytes of memory, and the Z8002, which supported only 16-bit addressing to allow 64 kilobytes of memory. This allowed the Z8002 to have eight fewer pins, shipping in a smaller 40-pin DIP format that made it less expensive to implement. Like the Zilog Z80, the Z8000's included built-in DRAM refresh circuitry.
The series was later expanded to include the Z8003 and Z8004, updated versions of the Z8001 and Z8002, respectively. These versions were designed to provide improved support for virtual memory, adding new status registers to indicate segmentation faults (test and set) and provide an abort capability.
The register set consisted of sixteen 16-bit general purpose registers, labeled R0 through R15. The registers can be concatenated into eight 32-bit registers, labeled RR0/RR2/../RR14, or into four 64-bit registers, labeled RQ0/RQ4/RQ8/RQ12. The first eight registers can be also subdivided into sixteen 8-bit registers, labeled RL0 though RL7 for the lower byte and RH0 through RH7 for the upper (high) byte. Register R15 is designated as stack pointer. On the Z8001, register R14 is used to add a fixed offset to the stack pointer, and the program counter is expanded to 32-bits to include a similar offset.
There was both a user mode ("normal") and a supervisor mode, selected by bit 14 in the flag register. In supervisor mode, the stack registers point to the system stack and all privileged instructions are available. In user mode, the stack registers point to the normal stack and all privileged instructions will generate a fault.
The Z8000 used a segmented memory map, with a 7-bit "segment number" and a 16-bit offset. Both numbers were represented by pins on the Z8001, meaning that it could directly address a 23-bit memory, or 8 MB. Internally, however, instructions could only directly access data within the 16-bit offset. This allowed the instruction format to be smaller; a system with direct access to a 23-bit address would need to read three bytes (24-bits) from memory for every address referred to in the code, thus requiring two reads on a 16-bit bus. With segments, the addresses needed only a single 16-bit read and the segment number only needed to be updated when the data crossed the 16-bit/64 kB boundaries. This can improve overall performance when the data can be arranged within 64 kB spans.
The optional 48-pin Z8010 memory management unit (MMU) expanded the memory map to 16 MB by translating the 23-bit address from the CPU to a 24-bit one. Internally, it held a list of 64 segments and an 8-bit pointer to the physical location of that segment in RAM. When the CPU attempted to access a particular segment, the Z8010 would translate that into an 8-bit address on the address bus, and then pass the 16-bit offset on unchanged. This allowed multiple programs to be spread out in physical RAM, each one given its own space to work in while believing they were accessing the entire 8 MB of RAM. The segments were variable length, expanding up to 64 kB in order to allow the entire memory to be accessed from 64 segments. If more than 64 segments were needed, multiple Z8010s could be used. The Z8010 was not available at the time of launch, and was ultimately nine months to a year late.
With the release of the Z8003/Z8004, the Z8015 was added to the lineup, adding paged memory support. The main difference is that the Z8015 breaks down the memory into 64 2 kB blocks, whereas the Z8010 broke memory into 64 variable-sized blocks, up to 64 kB each. Additionally, the Z8015 expands the segment number from 7 to 12 bits, and then using those as the most significant bits of the 23-bit overall address, overriding the upper bits of the original 16-bit offset. The advantage to this access scheme is that it is easy to read or write 2 kB blocks to a hard drive, so this pattern more closely matches what will ultimately happen on a segfault.
Z8000 CPU based systemsEdit
In the early 1980s, the Zilog Z8000 CPU was popular for desktop sized Unix machines. These low-cost Unix systems allowed small businesses to run a true multi-user system and share resources (disk, printers) before networking was common. They usually had only RS232 serial ports (4–16) and parallel printer ports instead of built in graphics, as was typical for servers of the time.
Z8000-based computer systems included Zilog's own System 8000 series, as well as other manufacturers:
- January 1980: C8002 made by Onyx Systems used the Z8001, ran Unix System III, came with C and FORTRAN 77 compilers, and had an available COBOL compiler as well. It had 8 serial ports, 1 QIC tape drive, a single 8" hard drive and cost ~$25k. The main processor offloaded the disk, tape, and serial IO operations to a Z80 processor on a second board.
- 1982: Olivetti M20, a non IBM-compatible PC that ran Olivetti PCOS, a derivative of COSMOS or CP/M.
- 1980-1986: Olivetti Linea 1 S1000, S6000, M30, M40, M50, M60, M70. These minicomputers from Olivetti all ran BCOS/COSMOS.
- 1985: the cancelled Commodore 900 computer project
- 1987–1989: the East German EAW (Elektro-Apparate-Werke) produced the Workstation/Multiuser System P8000 based on the East German U8000 clone of the Z8000.
The Zilog S8000 computer came out with a version of Unix called ZEUS (Zilog Enhanced Unix System). ZEUS was a port of Unix Version 7 and included what were referred to as 'the Berkeley Enhancements'. ZEUS included a version of COBOL called RM/COBOL (Ryan McFarland COBOL). The availability of RM/COBOL allowed many commercial applications to be quickly ported to the S8000 computer although this did not help its long term success. The S8000 did find some success with the IRS and tax preparers in United States, who used the model for processing of electronically filed tax returns.
There was a Z8000 version of the Xenix Operating System. Namco used the Z8000 series in its Pole Position and Pole Position II arcade games. The machines used two Z8002's, the 64 kB versions of the Z8000.
The reported inclusion of the device within military designs perhaps provides an explanation for the continued survival of the Z8000 today, in the shape of the Z16C01/02 Serial Communication Controllers (SCC). Also, the Standard Central Air Data Computer (SCADC) was utilizing the Z8002. The end of life notice from Zilog was sent in 2012.
While the Z8000 did see some use in the early 1980s, it was passed over for other designs relatively quickly.
Federico Faggin, then CEO of Zilog, later suggested this was due to Zilog's financing arrangement with Exxon's venture capital arm, Exxon Enterprises. Enterprises had made a number of investments in the computer field, and by the early 1980s was positioning itself as a competitor to IBM in the large system space. Faggin suggests that IBM thus saw Zilog as a competitor, and refused to consider the Z8000 as a result.
However, an examination of the choices available to designers in the early 1980s suggests there are more prosaic reasons the Z8000 was not more popular:
Comparing assembly language versions of the Byte Sieve, one sees that the 5.5 MHz Z8000's 1.1 seconds is impressive when compared to the 8-bit designs it replaced, including Zilog's 4 MHz Z80 at 6.8 seconds, and the popular 1 MHz MOS 6502 at 13.9. Even the newer 1 MHz Motorola 6809 was much slower, at 5.1 seconds. It also fares well against the 8 MHz Intel 8086 which turned in a time of 1.9 seconds, or the less expensive 5 MHz Intel 8088 at 4 seconds.
While the Intel processors were easily outperformed by the Z8001, they were packaged in 40-pin DIPs, which made them less expensive to implement than the 48-pin Z8001. The Z8002 also used a 40-pin package, but had a 16-bit address bus that could only access 64 kB of RAM, whereas the Intel processors had a 20-bit bus that could access 1 MB of RAM. Internally, the 23-bit addresses of the Z8000 were also more complex to process than Intel's simpler system using 16-bit base addresses and separate segment registers. For those looking for a low-cost option able to access (what was then) large amounts of memory, the Intel designs were competitive and available over a year earlier.
For those looking for pure performance, the Z8000 was the fastest CPU available in early 1979. But this was true only for a period of a few months. The 16/32-bit 8 Mhz Motorola 68000 came to market later the same year and turns in a time of 0.49 seconds on the same Sieve test, over twice as fast as the Z8000. Although it used an even larger 64-pin DIP layout, for those willing to move to more than 40-pins this was a small price to pay for what was by far the fastest processor of its era. Its 32-bit instructions and registers, combined with a 24-bit address bus with flat 16 MB addressing, also made it much more attractive to designers, something Faggin admits to.
To add to its problems, when the Z8000 was first released it contained a number of bugs. This was due to its complex instruction decoder, which, unlike most processors of the era, did not use microcode and was dependant on logic implemented directly in the CPU. This allowed the design to eliminate the microcode storage and the associated decoding logic, which reduced to the transistor count to 17,500. In contrast, the contemporary Intel 8088 used 29,000 transistors, while the Motorola 68000 of a few months later used 68,000.
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