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Hallows AG (direct your questions on your article here) 07:43, 10 March 2012 (UTC)

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Template:Inverse codon table, which you submitted to Articles for creation, has been created.
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A412 (Talk • C) 02:09, 12 March 2012 (UTC)

Your submission at Articles for creation

SOML, which you submitted to Articles for creation, has been created.
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WheresTristan 16:45, 9 April 2012 (UTC)

Talkback

Hello, 71.41.210.146. You have new messages at WheresTristan's talk page.
Message added 19:01, 9 April 2012 (UTC). You can remove this notice at any time by removing the {{Talkback}} or {{Tb}} template.

WheresTristan 19:01, 9 April 2012 (UTC)

Your submission at Articles for creation

VHB, which you submitted to Articles for creation, has been created.
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— The Earwig ^(talk) 05:39, 13 April 2012 (UTC)

Talkback

Hello, 71.41.210.146. You have new messages at Talk:TRIAC.
Message added 23:24, 29 April 2012 (UTC). You can remove this notice at any time by removing the {{Talkback}} or {{Tb}} template.

—Vitaltrust (talk) 23:24, 29 April 2012 (UTC)

Talkback #2

Hello, 71.41.210.146. You have new messages at Talk:TRIAC.
Message added 23:24, 29 April 2012 (UTC). You can remove this notice at any time by removing the {{Talkback}} or {{Tb}} template.

Sorry for my being late. — Vitaltrust (talk) 20:44, 10 May 2012 (UTC)

New message from Gareth Griffith-Jones

Hello, 71.41.210.146. You have new messages at Gareth Griffith-Jones's talk page.
Message added 09:22, 26 July 2012 (UTC). You can remove this notice at any time by removing the {{Talkback}} or {{Tb}} template.

Gareth Griffith-Jones (talk) 09:22, 26 July 2012 (UTC)

I have replied to your reply

-- Gareth Griffith-Jones (talk) 15:40, 26 July 2012 (UTC)

• Your final version looks fine now to a layman like me!
• I have replied to you, and copied'n'pasted to my Talk, your final version to the revision in order to complete our strand on my Talk. -- Gareth Griffith-Jones (talk) 07:22, 27 July 2012 (UTC)

EM6600 core

EM Microelectronics, part of The Swatch Group makes a series of ultra-low-power 4-bit microcontrollers, the EM66xx series. These are Mask ROM microcontrollers, although higher-power EEPROM versions (EM65xx) are available for development purposes.

These processors have 16-bit instructions, 12-bit ROM addresses (up to 4096 instruction words), and 7-bit (128 nibble) RAM space, of which up to 96 nibbles (48 bytes) are available as general-purpose RAM.

The instruction set is accumulator based, with most instructions operating on the accumulator and a specified RAM locations. Additionally, two RAM nibbles (0x6E=IXLow and 0x6F=IXHigh) make an 8-bit index register which may be used as a pointer register to select arbitrary RAM locations.

Three 12-bit program counters make up a hardware stack. This allows one level of subroutine calling plus an interrupt, or up to two levels of subroutine calls when interrupts are disabled.

A status register provides Z and C flags. All registers which write the accumulator also set the flags. Logical and move-to-accumulator instructions clear the carry bit. Stores do not affect the flags.

There are no add-with-carry instructions; the only instructions which depend on the carry flag are the conditional jumps.

Non-immediate operands use an 8-bit register specifier field. The most significant bit is the I bit:

• If I=0. the operand is one of 128 RAM nibbles, selected by the least significant seven bits.
• If I=1, the operand is specified by the IX register pair. The mnemonic has "X" appended, and no register operand is provided. (E.g. ADDX)

Because the unused register bits are conventionally set to 1, indexed instructions always end in hex FF and it would be easy to extend the architecture to 255 nibbles of RAM by assigning addresses 128–254.

ALU operations may also be modified by the S bit. If this is set, the menmonic has S appended, and the instruction performs a 5-bit rotate right through the carry bit after the ALU operation. The carry in is from the ALU result (0 for logical operations), and the carry out is the lsbit of the ALU result.

The 32 ALU instructions include all 16 2-input binary operations. Not all are documented, but it is clear that 4 bits of the instruction are used as a lookup table.

Judging by the small number of the 16 possible addition opcodes which are documented, there are additional undocumented instructions, but the pattern is not as clear.

1 5	1 4	1 3	1 2	1 1	1 0	9	8	7	6	5	4	3	2	1	0	Menmonic	Function
0	cond			address												Jumps
0	0 0 0			address												JMP addr	Unconditional jump
0	0 0 1			address												JPV1 addr	Jump if TestVar[1] = 1 (usually PA0)
0	0 1 0			address												JPV2 addr	Jump if TestVar[2] = 1 (usually PA1)
0	0 1 1			address												JPV3 addr	Jump if TestVar[3] = 1 (usually PA2)
0	1 0 0			address												JPC addr	Jump if Carry = 1
0	1 0 1			address												JPNC addr	Jump if Carry = 0
0	1 1 0			address												JPZ addr	Jump if Z = 1
0	1 1 1			address												JPNZ addr	Jump if Z = 0
1 0		opcode					S	I	reg							ALU operation: A ← source op A
1 0		opcode					0	0	reg							ALUop reg	A = reg op A
1 0		opcode					0	1	—							ALUopX	A = RAM[IX] op A
1 0		opcode					1	0	reg							ALUopS reg	A = SHR(reg op A)
1 0		opcode					1	1	—							ALUopXS	A = SHR(RAM[IX] op A)
1 0 0			opcode				S	I	reg							Addition operations (carry is set)
1 0 0			0 0 1 1				S	I	reg							INC[X][S] reg	A = source + 1
1 0 0			0 1 1 0				S	I	reg							SUB[X][S] reg	A = source − A = source + ~A + 1
1 0 0			1 0 0 1				S	I	reg							ADD[X][S] reg	A = source + A
1 0 0			1 1 0 0				S	I	reg							DEC[X][S] reg	A = source + 15
1 0 0			1 1 1 1				S	I	reg							SHL[X][S] reg	A = source + source
1 0 1			a b c d				S	I	reg							Bitwise logical operations
1 0 1			0 0 0 0				S	—								LDZ*	A = 0
1 0 1			0 0 0 1				S	I	reg							NOR[X][S] reg	A = ~(source | A)
1 0 1			0 0 1 0				S	I	reg							NORN[X][S] reg*	A = source & ~A = ~(~source | A)
1 0 1			0 0 1 1				S	I	reg							CPLR[X][S] reg	A = ~source
1 0 1			0 1 0 0				S	I	reg							ANDN[X][S] reg*	A = ~source & A
1 0 1			0 1 0 1				S	—								CPLA[S]	A = ~A
1 0 1			0 1 1 0				S	I	reg							XOR[X][S] reg	A = source ^ A
1 0 1			0 1 1 1				S	I	reg							NAND[X][S] reg	A = ~(source & A)
1 0 1			1 0 0 0				S	I	reg							AND[X][S] reg	A = source & A
1 0 1			1 0 0 1				S	I	reg							NXOR[X][S] reg	A = ~(source ^ A)
1 0 1			1 0 1 0				S	—								LDA[S]*	A = A
1 0 1			1 0 1 1				S	I	reg							NANDN[X][S] reg*	A = source | ~A = ~(~source & A)
1 0 1			1 1 0 0				S	I	reg							LDR[X][S] reg	A = source
1 0 1			1 1 0 1				S	I	reg							ORN[X][S] reg*	A = ~source | A
1 0 1			1 1 1 0				S	I	reg							OR[X][S] reg	A = source | A
1 0 1			1 1 1 1				S	—								LD1[S]*	A = 15
1 1 0			o	data				I	reg							Store: dest ← value
1 1 0			0	data				I	reg							STI[X] reg,data	Store immediate data in register
1 1 0			1	—				I	reg							STA[X] reg	Store accumulator in register
1 1 1 0				address												CALL addr	Increment SP, Jump to address
1 1 1 1				opcode				—								Miscellaneous instructions
1 1 1 1				0 0 0 0				—								NOP	No operation
1 1 1 1				0 0 1 0				—								RTI	Return from interrupt
1 1 1 1				0 1 0 0				—								HALT	Halt processor
1 1 1 1				1 0 0 0				—				data				LDI data	Load immediate to accumulator
1 1 1 1				1 0 1 0				—								RET	Return from subroutine

^*: Instruction not documented, extrapolated from others. Mnemonic hypothetical.

EM66xx 4-bit Micro controller family (PDF), 4.5, EM Microelectronic-Marin SA, October 2005, pp. 35–43