Wikipedia

SPARC T3

(Redirected from UltraSPARC T3)

The SPARC T3 microprocessor (previously known as UltraSPARC T3, codenamed Rainbow Falls,[1] and also known as UltraSPARC KT or Niagara-3 during development) is a multithreading, multi-core CPU produced by Oracle Corporation (previously Sun Microsystems).[2][3][4] Officially launched on 20 September 2010, it is a member of the SPARC family, and the successor to the UltraSPARC T2.[5]

SPARC T3
SPARC T3 micrograph
General information
Launched2010
Marketed byOracle Corporation
Designed bySun Microsystems
Performance
Max. CPU clock rate1.67 GHz
Cache
L1 cache(16+8) kB
L2 cache6 MB
Architecture and classification
Instruction setSPARC V9
Physical specifications
Cores
  • 8 or 16
Products, models, variants
Core name(s)
  • S2
History
Predecessor(s)UltraSPARC T2
Successor(s)SPARC T4

Performance edit

Overall single socket and multi-socket throughput increased with the T3 processor in systems, providing superior throughput with half the CPU socket requirements to its predecessor.

The throughput (SPEC CINT2006 rate) increased in single a socket T3-1 platform[6] in comparison to its predecessor T2+ processor in a dual-socket T5240 platform.[7]

Under simulated web serving workloads, dual-socket based SPARC T3 systems benchmarked better performance than quad-socket (previous generation) UltraSPARC T2+ systems (as well as competing dual and quad socket contemporary systems).[8]

History edit

 
SPARC T3 processor

Online IT publication The Register incorrectly reported in June 2008 that the microprocessor would have 16 cores, each with 16 threads. In September 2009 they published a roadmap that instead showed 8 threads per core.[9] During the Hot Chips 21 conference Sun revealed the chip has a total of 16 cores and 128 threads.[10][11] According to the ISSCC 2010 presentation:

"A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to maximize throughput. The 6MB L2 cache of 461GB/s and the 308-pin SerDes I/O of 2.4Tb/s support the required bandwidth. Six clock and four voltage domains, as well as power management and circuit techniques, optimize performance, power, variability and yield trade-offs across the 377mm2 die."[12]

Support for the UltraSPARC T3 was confirmed on July 16, 2010 when the ARCBot under Twitter noted unpublished PSARC/2010/274 which revealed a new "-xtarget value for UltraSPARC T3" being included in OpenSolaris.[13]

During Oracle OpenWorld in San Francisco on September 20, 2010, the processor was officially launched as the "SPARC T3" (dropping the "Ultra" prefix in its name), accompanied by new systems and new reported benchmarks claiming world-record performance.[4] Varied real-world application benchmarks were released with full system disclosures.[14][15][16] Internationally recognized SPEC benchmarks were also released with full system disclosures.[17][18] Oracle disclosed that SPARC T3 was built with a 40 nm process.[19]

Features edit

SPARC T3 features include:[19]

 
T3 microprocessor floorplan
  • 8 or 16 CPU cores
  • 8 hardware threads per core
  • 6 MB Level 2 cache
  • 2 embedded coherency controllers
  • 6 coherence links
  • 14 unidirectional lanes per coherence link
  • SMP to 4 sockets without glue circuitry
  • 4 DDR3 SDRAM memory channels
  • Embedded PCI Express I/O interfaces
  • Security co-processor on each core. Supports DES, 3DES, AES, RC4, SHA-1, SHA-256/384/512, Kasumi, Galois Field, MD5, RSA with up to 2048 key, ECC, CRC.
  • Hardware random number generator
  • 2 embedded 1GigE/10GigE interfaces
  • 2.4 Tbit/s aggregate throughput per socket

Systems edit

With the release of the SPARC T3 chip, the new brand of Oracle SPARC T-series servers was introduced to the market, effectively replacing CMT (UltraSPARC T2/T2 Plus) machines from the previous SPARC Enterprise product line. Fewer physical products from the former server line were refreshed with the T3 chip, reducing the total number of servers respectively to four:[20]

  • One Socket SPARC T3-1 2U Rack Server[21]
  • One Socket SPARC T3-1B Blade Server[22]
  • Two Socket SPARC T3-2 Server [23]
  • Four Socket SPARC T3-4 Server [24]

Virtualization edit

Like the prior T1, T2, and T2+ processors, the T3 supports Hyper-Privileged execution mode. The T3 supports up to 128 Oracle VM Server for SPARC domains (a feature formerly known as Logical Domains).[24]

Performance improvement versus T2 and T2+ edit

The SPARC T3 processor is effectively two T2+ processors on a single die.[25] The T3 has:

  • Double the cores (16) of a T2 or T2+
  • Double the 10Gig Ethernet ports (2) over a T2+
  • Double the crypto accelerator cores (16) over a T2 or T2+
  • Crypto engines support more algorithms than the T2 or T2+ including: DES, Triple DES, AES, RC4, SHA-1, SHA256/384/512, Kasumi, Galois Field, MD5, RSA to 2048 key, ECC, CRC32[19]
  • Over 1.9x Cryptography Performance Throughput Increase[26]
  • Faster DDR3 RAM interface over the T2 or T2+ DDR2 interface
  • Double the throughput[21]
  • Double the memory capacity[21]
  • Quadruple the I/O throughput[21]
  • Two PCIe 2.0 eight lane interfaces vs one PCIe former generation eight lane interface[25]

See also edit

References edit

  1. ^ RAINBOW FALLS, Sun's Next Generation CMT Processor, 2009-08, retrieved 2016-01-13
  2. ^ High-end server chips breaking records | Speeds and Feeds - CNET News
  3. ^ Sun, IBM push multicore boundaries
  4. ^ a b Oracle Unveils SPARC T3 Processor and SPARC T3 Systems
  5. ^ Oracle Unveils SPARC T3 Processor and SPARC T3 Systems
  6. ^ Oracle Corporation SPARC T3-1, 2008-03, retrieved 2011-07-19
  7. ^ Sun SPARC Enterprise T5240, 2008-03, retrieved 2010-11-25
  8. ^ SPECweb2005, 2008-03, retrieved 2011-07-19
  9. ^ "Sun's Sparc server roadmap revealed". The Register.
  10. ^ Sanjay Patel, Stephen Phillips and Allan Strong. "Sun's Next-Generation Multi-threaded Processor - Rainbow Falls: Sun's Next Generation CMT Processor Archived 2011-07-23 at the Wayback Machine". HOT CHIPS 21.
  11. ^ Stokes, Jon (February 9, 2010). "Two billion-transistor beasts: POWER7 and Niagara 3". Ars Technica.
  12. ^ J. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson, F. Schumacher, D. Greenhill, A. Leon, A. Strong. "A 40nm 16-Core 128-Thread CMT SPARC SoC Processor". ISSCC 2010.
  13. ^ Twitter / ARCbot: PSARC/2010/274 New compiler
  14. ^ Brian Whitney (September 27, 2010). "SPARC T3-1 Shows Capabilities Running Online Auction Benchmark with Oracle Fusion Middleware". BestPerf blog. Sun/Oracle. Archived from the original on 2011-03-08. Retrieved 2010-09-27.
  15. ^ "SPARC T3-1 Performance on PeopleSoft Enterprise Financials 9.0 Benchmark - BestPerf". blogs.sun.com. Archived from the original on 26 September 2010. Retrieved 22 May 2022.
  16. ^ "SPARC T3-1 Supports 13,000 Users on Financial Services and Enterprise Application Integration Running Siebel CRM 8.1.1 - BestPerf". blogs.sun.com. Archived from the original on 26 September 2010. Retrieved 22 May 2022.
  17. ^ Kevin Kelly (September 24, 2010). "SPARC T3-2 sets World Record on SPECjvm2008 Benchmark". BestPerf blog. Archived from the original on 2010-11-26. Retrieved 2010-09-27.
  18. ^ Kevin Kelly (September 20, 2010). "SPARC T3-4 Sets World Record Single Server Result on SPECjEnterprise2010 Benchmark". BestPerf blog. Archived from the original on 2010-09-24. Retrieved 2010-09-27.
  19. ^ a b c "SPARC T3 Processor Data Sheet" (PDF). 2010.
  20. ^ SPARC Servers
  21. ^ a b c d SPARC T3-1 | Web Infrastructure Server | Oracle
  22. ^ T3-1B | Best Blade for Infrastructure Apps | Oracle
  23. ^ SPARC T3-2 | Web Infrastructure Server | Oracle
  24. ^ a b SPARC T3-4 | Consolidation and Virtualization | Oracle
  25. ^ a b "SPARC T3 - some data - c0t0d0s0.org". Archived from the original on 2011-07-18. Retrieved 2010-10-01.
  26. ^ "SPARC T3 Cryptography Performance over 1.9x Increase in Throughput over UltraSPARC T2 Plus - BestPerf". blogs.sun.com. Archived from the original on 2 November 2010. Retrieved 22 May 2022.
Retrieved from "https://en.wikipedia.org/w/index.php?title=SPARC_T3&oldid=1107548081"