In electronics, a multi-level cell (MLC) is a memory cell capable of storing more than a single bit of information, compared to a single-level cell (SLC), which can store only one bit per memory cell. A memory cell typically consists of a single floating-gate MOSFET (metal–oxide–semiconductor field-effect transistor), thus multi-level cells reduce the number of MOSFETs required to store the same amount of data as single-level cells.
Triple-level cells (TLC) and quad-level cells (QLC) are versions of MLC memory, which can store three and four bits per cell respectively. The name "multi-level cell" is sometimes used specifically to refer to the "two-level cell". Overall, the memories are named as follows:
- Single-level cell or SLC (1 bit per cell)
- Multi-level cell or MLC (2 bits per cell), alternatively double-level cell or DLC
- Triple-level cell or TLC (3 bits per cell) or 3-Bit MLC
- Quad-level cell or QLC (4 bits per cell)
- Penta-level cell or PLC (5 bits per cell) – currently in development
Notice that this nomenclature can be misleading, since an "n-level cell" in fact uses 2n levels of charge to store n bits (see below).
Typically, as the "level" count increases, performance (speed and reliability) and consumer cost decrease; however, this correlation can vary between manufacturers.
Examples of MLC memories are MLC NAND flash, MLC PCM (phase-change memory), etc. For example, in SLC NAND flash technology, each cell can exist in one of the two states, storing one bit of information per cell. Most MLC NAND flash memory has four possible states per cell, so it can store two bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors. Multi-level cells that are designed for low error rates are sometimes called enterprise MLC (eMLC).
New technologies, such as multi-level cells and 3D Flash, and increased production volumes will continue to bring prices down.
Flash memory stores data in individual memory cells, which are made of floating-gate MOSFET transistors. Traditionally, each cell had two possible states (each with one voltage level), with each state representing either a one or a zero, so one bit of data was stored in each cell in so-called single-level cells, or SLC flash memory. SLC memory has the advantage of higher write speeds, lower power consumption and higher cell endurance. However, because SLC memory stores less data per cell than MLC memory, it costs more per megabyte of storage to manufacture. Due to higher transfer speeds and expected longer life, SLC flash technology is used in high-performance memory cards. In February 2016, a study was published that showed little difference in practice between the reliability of SLC and MLC.
A single-level cell (SLC) flash memory may have a lifetime of about 50,000 to 100,000 program/erase cycles.
A single-level cell represents a 1 when almost empty and a 0 when almost full. There is a region of uncertainty (a read margin) between the two possible states at which the data stored in the cell cannot be precisely read.
The primary benefit of MLC flash memory is its lower cost per unit of storage due to the higher data density, and memory-reading software can compensate for a larger bit error rate. The higher error rate necessitates an error-correcting code (ECC) that can correct multiple bit errors; for example, the SandForce SF-2500 flash controller can correct up to 55 bits per 512-byte sector with an unrecoverable read error rate of less than one sector per 1017 bits read. The most commonly used algorithm is Bose–Chaudhuri–Hocquenghem (BCH code). Other drawbacks of MLC NAND are lower write speeds, lower number of program/erase cycles and higher power consumption compared to SLC flash memory.
Read speeds can also be lower for MLC NAND than SLC due to the need to read the same data at a second threshold voltage to help resolve errors. TLC and QLC devices may need to read the same data up to 4 and 8 times respectively to obtain values that are correctable by ECC.
MLC flash may have a lifetime of about 1,000 to 10,000 program/erase cycles. This typically necessitates the use of a flash file system, which is designed around the limitations of flash memory, such as using wear leveling to extend the useful lifetime of the flash device.
The Intel 8087 used two-bits-per-cell technology, and in 1980 was one of the first devices on the market to use multi-level ROM cells. Intel later demonstrated 2-bit multi-level cell (MLC) NOR flash in 1997. NEC demonstrated quad-level cells in 1996, with a 64 Mbit flash memory chip storing 2 bits per cell. In 1997, NEC demonstrated a dynamic random-access memory (DRAM) chip with quad-level cells, holding a capacity of 4 Gbit. STMicroelectronics also demonstrated quad-level cells in 2000, with a 64 Mbit NOR flash memory chip.
MLC is used to refer to cells that store 2 bits per cell, using 4 charge values or levels. A 2-bit MLC has a single charge level assigned to every possible combination of ones and zeros, as follows: When close to 25% full, the cell represents a binary value of 11; when close to 50%, the cell represents a 01; when close to 75%, the cell represents a 00; and when close to 100%, the cell represents a 10. Once again, there is a region of uncertainty (read margin) between values, at which the data stored in the cell cannot be precisely read.
As of 2018,[update] nearly all commercial MLCs are planar-based (i.e. cells are built on silicon surface) and so subject to scaling limitations. To address this potential problem, the industry is already looking at technologies that can guarantee storage density increases beyond today’s limitations. One of the most promising is 3D Flash, where cells are stacked vertically, thereby avoiding the limitations of planar scaling.
In the past, a few memory devices went the other direction and used two cells per bit to give even lower bit error rates.
Enterprise MLC (eMLC) is a more expensive variant of MLC that is optimized for commercial use. It claims to last longer and be more reliable than normal MLCs while providing cost savings over traditional SLC drives. Although many SSD manufacturers have produced MLC drives intended for enterprise use, only Micron sells raw NAND Flash chips under this designation.
Samsung announced a type of NAND flash that stores 3 bits of information per cell, with 8 total voltage states (values or levels), coining the term "triple-level cell" ("TLC"). Samsung Electronics began mass-producing it in 2010, and it was first seen in Samsung's 840 Series SSDs. Samsung refers to this technology as 3-bit MLC. The negative aspects of MLC are amplified with TLC, but TLC benefits from still higher storage density and lower cost.
In 2013, Samsung introduced V-NAND (Vertical NAND, also known as 3D NAND) with triple-level cells, which had a memory capacity of 128 Gbit. They expanded their TLC V-NAND technology to 256 Gbit memory in 2015, and 512 Gbit in 2017.
Memory that stores 4 bits per cell is commonly referred to as quad-level cell (QLC), following the convention set by TLC. Prior to its invention, QLC referred to cells that can have 16 voltage states, i.e. ones that store 4 bits per cell.
SanDisk X4 flash memory cards, introduced in 2009, was one of the first products based on NAND memory that stores 4 bits per cell, commonly referred to as quad-level-cell (QLC), using 16 discrete charge levels (states) in each individual transistor. The QLC chips used in these memory cards were manufactured by Toshiba, SanDisk and SK Hynix.
In 2017, Toshiba introduced V-NAND memory chips with quad-level cells, which have a storage capacity of up to 768 Gbit. In 2018, ADATA, Intel, Micron and Samsung have launched some SSD products using QLC NAND memory.
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