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Three-dimensional integrated circuit

A three-dimensional integrated circuit (3D IC) is a MOS (metal-oxide semiconductor) integrated circuit (IC) manufactured by stacking silicon wafers or dies and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits, in microelectronics and nanoelectronics.

3D integrated circuits can be classified by their level of interconnect hierarchy at the global (package), intermediate (bond pad) and local (transistor) level [1] In general, 3D integration is a broad term that includes such technologies as 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs (3D-SICs), monolithic 3D ICs; 3D heterogeneous integration; and 3D systems integration.[2][3]

International organizations such as the Jisso Technology Roadmap Committee (JIC) and the International Technology Roadmap for Semiconductors (ITRS) have worked to classify the various 3D integration technologies to further the establishment of standards and roadmaps of 3D integration.[4] As of the 2010s, 3D ICs are widely used for NAND flash memory in mobile devices.

Contents

TypesEdit

3D ICs vs. 3D packagingEdit

3D Packaging refers to 3D integration schemes that rely on traditional methods of interconnect such as wire bonding and flip chip to achieve vertical stacks. 3D packaging can be disseminated further into 3D system in package (3D SiP) and 3D wafer level package (3D WLP). Stacked memory die interconnected with wire bonds, and package on package (PoP) configurations interconnected with either wire bonds, or flip chips are 3D SiPs that have been in mainstream manufacturing for some time and have a well established infrastructure. PoP is used for vertically integrating disparate technologies such as 3D WLP uses wafer level processes such as redistribution layers (RDL) and wafer bumping processes to form interconnects.

2.5D interposer is also a 3D WLP that interconnects die side-side on a silicon, glass or organic interposer using TSVs and RDL. In all types of 3D Packaging, chips in the package communicate using off-chip signaling, much as if they were mounted in separate packages on a normal circuit board.

3D ICs can be divided into 3D Stacked ICs (3D SIC), which refers to stacking IC chips using TSV interconnects, and monolithic 3D ICs, which use fab processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy as set forth by the ITRS, this results in direct vertical interconnects between device layers. The first examples of a monolithic approach are seen in Samsung's 3D V-NAND devices.[5]

As of the 2010s, 3D IC packages are widely used for NAND flash memory in mobile devices.[6]

 
One master die and three slave dies

3D SiCsEdit

The digital electronics market requires a higher density semiconductor memory chip to cater to recently released CPU components, and the multiple die stacking technique has been suggested as a solution to this problem. JEDEC disclosed the upcoming DRAM technology includes the "3D SiC" die stacking plan at "Server Memory Forum", November 1–2, 2011, Santa Clara, CA. In August 2014, Samsung Electronics started producing 64 GB SDRAM modules for servers based on emerging DDR4 (double-data rate 4) memory using 3D TSV package technology.[7] Newer proposed standards for 3D stacked DRAM include Wide I/O, Wide I/O 2, Hybrid Memory Cube, High Bandwidth Memory.

Monolithic 3D ICsEdit

Monolithic 3D ICs are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias. Process temperature limitations are addressed by partitioning the transistor fabrication to two phases. A high temperature phase which is done before layer transfer follow by a layer transfer use ion-cut, also known as layer transfer, which has been used to produce Silicon on Insulator (SOI) wafers for the past two decades. Multiple thin (10s–100s nanometer scale) layers of virtually defect-free Silicon can be created by utilizing low temperature (<400℃) bond and cleave techniques, and placed on top of active transistor circuitry. Follow by finalizing the transistors using etch and deposition processes. This monolithic 3D IC technology has been researched at Stanford University under a DARPA-sponsored grant.

CEA-Leti is also developing monolithic 3D IC approaches, called sequential 3D IC. In 2014, the French research institute introduced its CoolCube™, a low-temperature process flow that provides a true path to 3DVLSI.[8] At Stanford University, researchers are designing monolithic 3D ICs using carbon nanotube (CNT) structures vs. silicon using a wafer-scale low temperature CNT transfer processes that can be done at 120℃.[9]

In general, monolithic 3D ICs are still a developing technology and are considered by most to be several years away from production.

Manufacturing technologies for 3D SiCsEdit

There are several methods for 3D IC design, including recrystallization and wafer bonding methods. There are two major types of wafer bonding, Cu-Cu connections (copper-to-copper connections)[10] and through-silicon via (TSV). As of 2014, a number of memory products such as High Bandwidth Memory (HBM) and the Hybrid Memory Cube have been launched that implement 3D IC stacking with TSVs. There are a number of key stacking approaches being implemented and explored. These include die-to-die, die-to-wafer, and wafer-to-wafer.

Die-to-Die
Electronic components are built on multiple die, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding. One advantage of die-to-die is that each component die can be tested first, so that one bad die does not ruin an entire stack.[11] Moreover, each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance (e.g. matching multiple dice from the low power process corner for a mobile application).
Die-to-Wafer
Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dice are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional die may be added to the stacks before dicing.
Wafer-to-Wafer
Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These "through-silicon vias" (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad. Wafer-to-wafer bonding can reduce yields, since if any 1 of N chips in a 3D IC are defective, the entire 3D IC will be defective. Moreover, the wafers must be the same size, but many exotic materials (e.g. III-Vs) are manufactured on much smaller wafers than CMOS logic or DRAM (typically 300 mm), complicating heterogeneous integration.

BenefitsEdit

While traditional CMOS scaling processes improves signal propagation speed, scaling from current manufacturing and chip-design technologies is becoming more difficult and costly, in part because of power-density constraints, and in part because interconnects do not become faster while transistors do.[12] 3D ICs address the scaling challenge by stacking 2D dies and connecting them in the 3rd dimension. This promises to speed up communication between layered chips, compared to planar layout.[13] 3D ICs promise many significant benefits, including:

Footprint
More functionality fits into a small space. This extends Moore's law and enables a new generation of tiny but powerful devices.
Cost
Partitioning a large chip into multiple smaller dies with 3D stacking can improve the yield and reduce the fabrication cost if individual dies are tested separately.[14][15]
Heterogeneous integration
Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Moreover, components with incompatible manufacturing could be combined in a single 3D IC.[16][3]
Shorter interconnect
The average wire length is reduced. Common figures reported by researchers are on the order of 10–15%, but this reduction mostly applies to longer interconnect, which may affect circuit delay by a greater amount. Given that 3D wires have much higher capacitance than conventional in-die wires, circuit delay may or may not improve.
Power
Keeping a signal on-chip can reduce its power consumption by 10–100 times.[17] Shorter wires also reduce power consumption by producing less parasitic capacitance.[18] Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.
Design
The vertical dimension adds a higher order of connectivity and offers new design possibilities.[3]
Circuit security
3D integration can achieve security through obscurity; the stacked structure complicates attempts to reverse engineer the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.[19] Moreover, 3D integration allows to integrate dedicated, system monitor-like features in separate layers.[3] The objective here is to implement some kind of hardware firewall for any commodity components/chips to be monitored at runtime, seeking to protect the whole electronic system against run-time attacks as well as malicious hardware modifications.
Bandwidth
3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth buses between functional blocks in different layers. A typical example would be a processor+memory 3D stack, with the cache memory stacked on top of the processor. This arrangement allows a bus much wider than the typical 128 or 256 bits between the cache and processor.[20] Wide buses in turn alleviate the memory wall problem.[21]

ChallengesEdit

Because this technology is new it carries new challenges, including:

Cost
While cost is a benefit when compared with scaling, it has also been identified as a challenge to the commercialization of 3D ICs in mainstream consumer applications. However, work is being done to address this. Although 3D technology is new and fairly complex, the cost of the manufacturing process is surprisingly straightforward when broken down into the activities that build up the entire process. By analyzing the combination of activities that lay at the base, cost drivers can be identified. Once the cost drivers are identified, it becomes a less complicated endeavor to determine where the majority of cost comes from and, more importantly, where cost has the potential to be reduced.[22]
Yield
Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be commercially viable, defects could be repaired or tolerated, or defect density can be improved.[23][24]
Heat
Heat building up within the stack must be dissipated. This is an inevitable issue as electrical proximity correlates with thermal proximity. Specific thermal hotspots must be more carefully managed.
Design complexity
Taking full advantage of 3D integration requires sophisticated design techniques and new CAD tools.[25]
TSV-introduced overhead
TSVs are large compared to gates and impact floorplans. At the 45 nm technology node, the area footprint of a 10μm x 10μm TSV is comparable to that of about 50 gates.[26] Furthermore, manufacturability demands landing pads and keep-out zones which further increase TSV area footprint. Depending on the technology choices, TSVs block some subset of layout resources.[26] Via-first TSVs are manufactured before metallization, thus occupy the device layer and result in placement obstacles. Via-last TSVs are manufactured after metallization and pass through the chip. Thus, they occupy both the device and metal layers, resulting in placement and routing obstacles. While the usage of TSVs is generally expected to reduce wirelength, this depends on the number of TSVs and their characteristics.[26] Also, the granularity of inter-die partitioning impacts wirelength. It typically decreases for moderate (blocks with 20-100 modules) and coarse (block-level partitioning) granularities, but increases for fine (gate-level partitioning) granularities.[26]
Testing
To achieve high overall yield and reduce costs, separate testing of independent dies is essential.[24][27] However, tight integration between adjacent active layers in 3D ICs entails a significant amount of interconnect between different sections of the same circuit module that were partitioned to different dies. Aside from the massive overhead introduced by required TSVs, sections of such a module, e.g., a multiplier, cannot be independently tested by conventional techniques. This particularly applies to timing-critical paths laid out in 3D.
Lack of standards
There are few standards for TSV-based 3D IC design, manufacturing, and packaging, although this issue is being addressed.[28][29] In addition, there are many integration options being explored such as via-last, via-first, via-middle;[30] interposers[31] or direct bonding; etc.
Heterogeneous integration supply chain
In heterogeneously integrated systems, the delay of one part from one of the different parts suppliers delays the delivery of the whole product, and so delays the revenue for each of the 3D IC part suppliers.
Lack of clearly defined ownership
It is unclear who should own the 3D IC integration and packaging/assembly. It could be assembly houses like ASE or the product OEMs.

Design stylesEdit

Depending on partitioning granularity, different design styles can be distinguished. Gate-level integration faces multiple challenges and currently appears less practical than block-level integration.[32]

Gate-level integration
This style partitions standard cells between multiple dies. It promises wirelength reduction and great flexibility. However, wirelength reduction may be undermined unless modules of certain minimal size are preserved. On the other hand, its adverse effects include the massive number of necessary TSVs for interconnects. This design style requires 3D place-and-route tools, which are unavailable yet. Also, partitioning a design block across multiple dies implies that it cannot be fully tested before die stacking. After die stacking (post-bond testing), a single failed die can render several good dies unusable, undermining yield. This style also amplifies the impact of process variation, especially inter-die variation. In fact, a 3D layout may yield more poorly than the same circuit laid out in 2D, contrary to the original promise of 3D IC integration.[33] Furthermore, this design style requires to redesign available Intellectual Property, since existing IP blocks and EDA tools do not provision for 3D integration.
Block-level integration
This style assigns entire design blocks to separate dies. Design blocks subsume most of the netlist connectivity and are linked by a small number of global interconnects. Therefore, block-level integration promises to reduce TSV overhead. Sophisticated 3D systems combining heterogeneous dies require distinct manufacturing processes at different technology nodes for fast and low-power random logic, several memory types, analog and RF circuits, etc. Block-level integration, which allows separate and optimized manufacturing processes, thus appears crucial for 3D integration. Furthermore, this style might facilitate the transition from current 2D design towards 3D IC design. Basically, 3D-aware tools are only needed for partitioning and thermal analysis.[34] Separate dies will be designed using (adapted) 2D tools and 2D blocks. This is motivated by the broad availability of reliable IP blocks. It is more convenient to use available 2D IP blocks and to place the mandatory TSVs in the unoccupied space between blocks instead of redesigning IP blocks and embedding TSVs.[32] Design-for-testability structures are a key component of IP blocks and can therefore be used to facilitate testing for 3D ICs. Also, critical paths can be mostly embedded within 2D blocks, which limits the impact of TSV and inter-die variation on manufacturing yield. Finally, modern chip design often requires last-minute engineering changes. Restricting the impact of such changes to single dies is essential to limit cost.

HistoryEdit

The concept of a three-dimensional MOS (metal-oxide-semiconductor) integrated circuit was proposed by Texas Instruments researchers Robert W. Haisty, Rowland E. Johnson and Edward W. Mehal in 1964.[35] In 1969, the concept of a three-dimensional MOS integrated circuit memory chip was proposed by NEC researchers Katsuhiro Onoda, Ryo Igarashi, Toshio Wada, Sho Nakanuma and Toru Tsujide.[36]

Early demonstrations (1980s–1990s)Edit

3D ICs were first successfully demonstrated in 1980s Japan, where research and development (R&D) on 3D ICs was initiated in 1981 with the "Three Dimensional Circuit Element R&D Project" by the Research and Development Association for Future (New) Electron Devices.[37] There were initially two forms of 3D IC design being investigated, recrystallization and wafer bonding, with the earliest successful demonstrations using recrystallization.[10] In 1983, a Fujitsu research team including S. Kawamura, Nobuo Sasaki and T. Iwai successfully fabricated a three-dimensional CMOS integrated circuit, using laser beam recrystallization. It consisted of a structure in which one type of transistor is fabricated directly above a transistor of the opposite type, with separate gates and an insulator in between. A double-layer of silicon nitride and phosphosilicate glass (PSG) film was used as an intermediate insulating layer between the top and bottom devices. This provided the basis for realizing a multi-layered 3D device composed of vertically-stacked transistors, with separate gates and an insulating layer in between.[38] The following year, the same Fujitsu research team fabricated a 3D gate array with vertically-stacked dual SOI/CMOS structure using beam recrystallization.[39]

In 1986, Mitsubishi Electric researchers Yoichi Akasaka and Tadashi Nishimura laid out the basic concepts and proposed technologies for 3D ICs.[40][41] The following year, a Mitsubishi research team including Nishimura, Akasaka and Osaka University graduate Yasuo Inoue fabricated an image signal processor (ISP) on a 3D IC, with an array of photosensors, CMOS A-to-D converters, arithmetic logic units (ALU) and shift registers arranged in a three-layer structure.[42] In 1989, an NEC research team led by Yoshihiro Hayashi fabricated a 3D IC with a four-layer structure using laser beam crystallisation.[43][40] In 1990, a Matsushita research team including K. Yamazaki, Y. Itoh and A. Wada fabricated a parallel image signal processor on a four-layer 3D IC, with SOI (silicon-on-insulator) layers formed by laser recrystallization, and the four layers consisting of an optical sensor, level detector, memory and ALU.[44]

The most common form of 3D IC design is wafer bonding.[10] Wafer bonding was initially called "cumulatively bonded IC" (CUBIC), which began development in 1981 with the "Three Dimensional Circuit Element R&D Project" in Japan and was completed in 1990 by Yoshihiro Hayashi's NEC research team, who demonstrated a method where several thin-film devices are bonded cumulatively, which would allow a large number of device layers. They proposed fabrication of separate devices in separate wafers, reduction in the thickness of the wafers, providing front and back leads, and connecting the thinned die to each other. They used CUBIC technology to fabricate and test a two active layer device in a top-to-bottom fashion, having a bulk-Si NMOS FET lower layer and a thinned NMOS FET upper layer, and proposed CUBIC technology that could fabricate 3D ICs with more than three active layers.[40][37][45]

The first 3D IC stacked chips fabricated with a through-silicon via (TSV) process were invented in 1980s Japan. Hitachi filed a Japanese patent in 1983, followed by Fujitsu in 1984. In 1986, a Japanese patent filed by Fujitsu described a stacked chip structure using TSV.[37] In 1989, Mitsumasa Koyonagi of Tohoku University pioneered the technique of wafer-to-wafer bonding with TSV, which he used to fabricate a 3D LSI chip in 1989.[37][46][47] In 1999, the Association of Super-Advanced Electronics Technologies (ASET) in Japan began funding the development of 3D IC chips using TSV technology, called the "R&D on High Density Electronic System Integration Technology" project.[37][48] The term "through-silicon via" (TSV) was coined by Tru-Si Technologies researchers Sergey Savastiouk, O. Siniaguine, and E. Korczynski, who proposed a TSV method for a 3D wafer-level packaging (WLP) solution in 2000.[49]

Copper-to-copper wafer bonding, also called Cu-Cu connections or Cu-Cu wafer bonding, was developed at MIT by a research team consisting of Andy Fan, Adnan-ur Rahman and Rafael Reif in 1999.[10][50] Reif and Fan further investigated Cu-Cu wafer bonding with other MIT researchers including Kuan-Neng Chen, Shamik Das, Chuan Seng Tan and Nisha Checka during 2001–2002.[10]

In Europe, Fraunhofer IFT and Siemens made pioneering contributions to 3D IC integration. Starting 1988 they were fabricating 3D CMOS ICs based on re-crystallization of Poly-Silicon. In the 1990´s, the Munich team with a.o., Manfred Engelhardt, Armin Klumpp and Peter Ramm proposed new approaches based on low temperature wafer bonding and vertical integration of IC devices using inter-chip vias (later called TSV), leading to pioneering patents. Ramm initiated industry-academic consortia for production of relevant 3D integration technologies. In the cooperative VSI® project between Siemens and Fraunhofer they were the first to demonstrate a complete industrial 3D IC stacking process (1993-1996). With his Siemens and Fraunhofer colleagues, Ramm published results showing the details of key processes such as 3D metallization [DUMIC 95][ME 97] and at ECTC 1995 they presented early investigations on stacked memories on processors [Trans. CPMT 96].

Demonstrations (2000s)Edit

The Koyanagi Group at Tohoku University, led by Mitsumasa Koyanagi, used TSV technology to fabricate a three-layer memory chip in 2000, a three-layer artificial retina chip in 2001, a three-layer microprocessor in 2002, and a ten-layer memory chip in 2005.[46] The same year, a Stanford University research team consisting of Kaustav Banerjee, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat presented a novel 3D chip design that exploits the vertical dimension to alleviate the interconnect related problems and facilitates heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design.[51][52]

In the early 2000´s the team of Fraunhofer and Infineon Munich investigated 3D TSV technologies with particular focus on die-to-substrate stacking and initiated the European Integrating Projects e-CUBES®, as a first European 3D technology platform, and e-BRAINS with a.o., Infineon, Siemens, EPFL, IMEC and Tyndall [www.e-brains.org] where heterogeneous 3D integrated system demonstrators were fabricated and evaluated. A particular focus of the e-BRAINS project was the development of novel low-temperature processes for highly reliable 3D integrated sensor systems.

In 2004, Tezzaron Semiconductor[53] built working 3D devices from six different designs.[54] The chips were built in two layers with "via-first" tungsten TSVs for vertical interconnection. Two wafers were stacked face-to-face and bonded with a copper process. The top wafer was thinned and the two-wafer stack was then diced into chips. The first chip tested was a simple memory register, but the most notable of the set was an 8051 processor/memory stack that exhibited much higher speed and lower power consumption than an analogous 2D assembly.

In 2004, Intel presented a 3D version of the Pentium 4 CPU.[55] The chip was manufactured with two dies using face-to-face stacking, which allowed a dense via structure. Backside TSVs are used for I/O and power supply. For the 3D floorplan, designers manually arranged functional blocks in each die aiming for power reduction and performance improvement. Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspots. The 3D design provides 15% performance improvement (due to eliminated pipeline stages) and 15% power saving (due to eliminated repeaters and reduced wiring) compared to the 2D Pentium 4.

The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory. Due to the high demand for memory bandwidth, a traditional I/O approach would consume 10 to 25 W.[27] To improve upon that, Intel designers implemented a TSV-based memory bus. Each core is connected to one memory tile in the SRAM die with a link that provides 12 GB/s bandwidth, resulting in a total bandwidth of 1 TB/s while consuming only 2.2 W.

An academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students. The chip runs at a 1.4 GHz and it was designed for optimized vertical processing between the stacked chips which gives the 3D processor abilities that the traditional one layered chip could not reach.[56] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in harmony without any obstacles that would interfere with a piece of information traveling from one layer to another.[57]

In ISSCC 2012, two 3D-IC-based multi-core designs using GlobalFoundries' 130 nm process and Tezzaron's FaStack technology were presented and demonstrated. 3D-MAPS,[58] a 64 custom core implementation with two-logic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology. The second prototype was from the Department of Electrical Engineering and Computer Science at University of Michigan called Centip3De, a near-threshold design based on ARM Cortex-M3 cores.

Commercialization (2000s–2010s)Edit

In 2001, a Toshiba research team including T. Imoto, M. Matsui and C. Takubo developed a "System Block Module" wafer bonding process for manufacturing 3D IC packages.[59][60] The earliest known commercial use of a 3D IC chip was in Sony's PlayStation Portable (PSP) handheld game console, released in 2004. The PSP hardware includes eDRAM (embedded DRAM) memory manufactured by Toshiba in a 3D system-in-package chip with two dies stacked vertically.[6] Toshiba called it "semi-embedded DRAM" at the time, before later calling it a stacked "chip-on-chip" (CoC) solution.[6][61]

In April 2007, Toshiba commercialized an eight-layer 3D IC, the 16 GB THGAM embedded NAND flash memory chip, which was manufactured with eight stacked 2 GB NAND flash chips.[62] In September 2007, Hynix introduced 24-layer 3D IC technology, with a 16 GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process.[63] Toshiba also used an eight-layer 3D IC for their 32 GB THGBM flash chip in 2008.[64] In 2010, Toshiba used a 16-layer 3D IC for their 128 GB THGBM2 flash chip, which was manufactured with 16 stacked 8 GB chips.[65] In the 2010s, 3D ICs came into widespread commercial use in the form of multi-chip package and package on package solutions for NAND flash memory in mobile devices.[6]

Elpida Memory developed the first 8 GB DRAM chip (stacked with four DDR3 SDRAM dies) in September 2009, and released it in June 2011.[66] TSMC announced plans for 3D IC production with TSV technology in January 2010.[66] In 2011, SK Hynix introduced 16 GB DDR3 SDRAM (40 nm class) using TSV technology,[67] Samsung Electronics introduced 3D-stacked 32 GB DDR3 (30 nm class) based on TSV in September, and then Samsung and Micron Technology announced TSV-based Hybrid Memory Cube (HMC) technology in October.[66] High Bandwidth Memory (HBM), developed by Samsung, AMD, and SK Hynix, uses stacked chips and TSVs. The first HBM memory chip was manufactured by SK Hynix in 2013.[67]

In 2017, Samsung Electronics combined 3D IC stacking with its 3D V-NAND technology (based on charge trap flash technology), manufacturing its 512 GB KLUFG8R1EM flash memory chip with eight stacked 64-layer V-NAND chips.[68] In 2019, Samsung produced a 1 TB flash chip with 16-layer V-NAND dies.[69] 96-layer chips are coming in 2019.[70][71] As of 2018, Intel is considering the use of 3D ICs to improve performance.[72]

See alsoEdit

NotesEdit

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  20. ^ Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, and Hsien-Hsin S. Lee. "An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth". In Proceedings of the 16th International Symposium on High-Performance Computer Architecture, pp.429-440, Bangalore, India, January 2010.
  21. ^ "Predicting the Performance of a 3D Processor-Memory Chip Stack" Jacob, P., McDonald, J.F. et al.Design & Test of Computers, IEEE Volume 22, Issue 6, Nov.–Dec. 2005 Page(s):540–547
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ReferencesEdit

Further readingEdit

  • Philip Garrou, Christopher Bower, Peter Ramm: Handbook of 3D Integration, Technology and Applications of 3D Integrated Circuits Vol. 1 and Vol. 2, Wiley-VCH, Weinheim 2008, ISBN 978-3-527-32034-9.
  • Yuan Xie, Jason Cong, Sachin Sapatnekar: Three-Dimensional Integrated Circuit Design: Eda, Design And Microarchitectures, Publisher: Springer, ISBN 1-4419-0783-1, ISBN 978-1-4419-0783-7,978-1441907837, Publishing Date: Dec 2009
  • Philip Garrou, Mitsumasa Koyanagi, Peter Ramm: Handbook of 3D Integration, 3D Process Technology Vol. 3, Wiley-VCH, Weinheim 2014, ISBN 978-3-527-33466-7.
  • Paul D. Franzon, Erik Jan Marinissen, Muhannad S. Bakir, Philip Garrou, Mitsumasa Koyanagi, Peter Ramm: Handbook of 3D Integration: "Design, Test, and Thermal Management of 3D Integrated Circuits", Vol. 4, Wiley-VCH, Weinheim 2019, ISBN 978-3-527-33855-9.

External linksEdit