Template:AMD x86 CPU features

The following table shows features of AMD's CPUs (see also: List of AMD microprocessors).

Codename Server High-end SledgeHammer Athens Egypt Santa Rosa Barcelona Shanghai Istanbul Magny-Cours Interlagos Abu Dhabi Milan
Mainstream Palomino Thoroughbred Barton SledgeHammer Troy Italy Santa Rosa Barcelona Shanghai Istanbul Lisbon Valencia Seoul Naples Rome
Entry SledgeHammer Venus,
Venus
Denmark Santa Ana Budapest Suzuka Zurich Delhi
Desktop High-end SledgeHammer Windsor Whitehaven Colfax Castle Peak
Mainstream Am386 Am486 Am5x86 SSA/5 5k86 K6 Model 6 Little Foot Chomper Extended,
Chomper
Sharptooth Argon Orion,
Pluto
Thunderbird,
Spitfire
Palomino,
Morgan
Thoroughbred,
Applebred,
Thoroughbred-B
Barton,
Thorton,
Barton,
Thorton
ClawHammer,
ClawHammer,
Newcastle
Winchester San Diego,
San Diego,
Venice,
Palermo
Toledo,
Manchester, Toledo,
Manchester, Toledo
Windsor,
Windsor,
Orleans
Brisbane,
Lima,
Brisbane,
Sparta
Agena, Toliman,
Kuma
Deneb, TWKR, Propus, Heka, Callisto, Regor,
Propus, Rana, Regor, Sargas,
Regor, Sargas
Thuban, Zosma,
Zosma
Zambezi Vishera Summit Ridge Pinnacle Ridge Matisse Vermeer
Entry ClawHammer,
Newcastle,
Paris
Palermo Venice,
Palermo
Manila, Manila
Basic GX[a] GXi[a] GXm[b]
Mobile Performance Thoroughbred Barton ClawHammer Newark Champlain,
Champlain
Marketed under AMD APU
Mainstream K6-III-P K6-III+,
K6-2+
Corvette Thoroughbred,
Thoroughbred
Barton Odessa Oakville Lancaster Trinidad,
Taylor,
Richmond
Lion,
Tyler,
Tyler
Caspian,
Caspian
Champlain,
Champlain,
Geneva
Entry Spitfire Camaro Applebred Dublin,
Dublin,
Dublin
Georgetown,
Sonora
Albany,
Roma
Keene Sable,
Sable,
Conesus,
Sherman,
Huron
Caspian Champlain,
Geneva
Basic Caspian Geneva GX[a] GXi[a] GXm[b] GXLV[c] GX1 SC GX2[d] LX NX
Embedded Champlain,
Geneva
Snowy Owl
Platform High, standard, and low power Low and ultra-low power
IGP N/A Yes N/A
Released March 1991 April 1993 November 1995 March 1996 October 1996 April 1997 January 1998 May 1998 February 1999 April 2000 June 1999 November 1999 June 2000 October 2001 June 2002 February 2003 September 2003 August 2004 April 2005 May 2005 May 2006 December 2006 September 2007 November 2008 June 2009 March 2010 October 2011 October 2012 March 2017 April 2018 July 2019 November 2020 February 1997 1997 1998 1999 April 2000 September 2000 June 2002 May 2005 May 2004
CPU microarchitecture Am386 Am486 Am5x86 SSA/5 5k86 K6 K6-2 K6-III K6-III+ K7 K8 K10 Bulldozer Piledriver Zen Zen+ Zen 2 Zen 3 MediaGX Thoroughbred
ISA x86-32 x86-32, x86-64 x86-64 x86-32
Socket Server High-end N/A 940 N/A 940 N/A F N/A F F+ G34 N/A N/A
Mainstream N/A A C32 SP3
Entry N/A 939 940, 939 AM2 AM2+ AM3, F+ N/A AM3+
Basic N/A
Micro
Desktop High-end N/A 940 N/A 1207 FX N/A TR4 sTRX4
Mainstream 1, 2, 3 5, 7 7 Super 7 N/A Slot A Slot A, A A 939 AM2 AM2+ AM2+, AM3 N/A AM3+ AM4
Entry N/A 754 N/A
Basic N/A N/A
Other Super 7 A A, 563 754 N/A S1 S1, ASB2 N/A SP4 A
PCI Express version N/A 1.1, 2.0 2.0 3.0 4.0
Fab. (nm) AMD 1500
(bulk)
AMD 800
(bulk)
AMD 700
(bulk)
AMD 500
(bulk))
AMD 350
(bulk)
AMD 350
(bulk)
AMD 500
(bulk)
AMD 350
(bulk)
AMD 350
(bulk)
AMD 250
(bulk)
AMD 180
(bulk)
AMD 250
(bulk)
AMD 180
(bulk)
AMD 130
(SOI)
AMD 90
(SOI)
AMD, GF 65
(strained SOI)
AMD, GF 45
(strained SOI)
GF 45
(strained SOI)
GF 32SHP
(HKMG SOI)
GF 14LPP
(FinFET bulk)
GF 12LP
(FinFET bulk)
TSMC N7
(FinFET bulk)
IBM 400
(bulk)
IBM 350
(bulk)
IBM, NS 350
(bulk)
NS 250
(bulk)
NS 180
(bulk)
TSMC 150
(bulk)
TSMC 130
(bulk)
AMD 130
(SOI)
Die area (mm2)
Min. thermal design power, TDP 0.32
Max. thermal design power, TDP 3.03 50 65 72 79.2 104 67 104 110 62 125 89 125 137 140 220 180 250 280 105 2.5 1.2 0.9 3.9
Max. stock base clock (MHz) 40 120 160 100 133 233 300 550 475 550 700 1000 1400 1733 2200 2333 2600 2200 3000 2800 2200 3200 3100 2600 3700 2800 3900 4700 3800 3700 3900 3800 150 180 300 266 330 300 400 600 1800
Max. CPUs per node[e] 1 2 8 1 8 1 8 1 8 4 2 1 1
Max. cores per CPU 1 2 4 6 12 16 32 64 16 1
Max. threads per core 1 2 1
Integer structure 2+2 2+1+1 3+3 2+2 4+2 4+2+1 2+2+1+1+1+1 1+1 3+3
Basic architecture level i386 i486 i586 pentium-mmx PREFETCHW PREFETCHW and i686[f] PAE NX bit 64-bit LAHF/SAHF[g] CMPXCHG16B AMD-V[h] RVI and ABM IOMMU[i] IOMMU[j], BMI1, AES-NI, CLMUL and F16C i586 CMOV CMOV and PREFETCHW PAE
TBM N/A Yes N/A
AVIC, BMI2, MOVBE, ADX, SHA, RDRAND/RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO N/A Yes
x2APIC, WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT N/A Yes
FPUs per core 0 0, 1 1 0.5 1 1
Pipes per FPU 1 2 1 2
FPU pipe width 80-bit 80-bit, 128-bit 128-bit 256-bit 80-bit
CPU instruction set SIMD level N/A MMX 3DNow! 3DNow!+ Enhanced 3DNow! SSE SSE2 SSE3 SSE4a[k] AVX AVX2 N/A MMX Inverse 3DNow! SSE
3DNow! N/A 3DNow! 3DNow!+ N/A N/A Inverse 3DNow! 3DNow!+
PREFETCH/PREFETCHW N/A Yes N/A Yes
FMA4, LWP, and XOP N/A Yes N/A N/A
FMA3 N/A Yes
Max. total L1 cache (KiB) 0 8 16 24 64 128 256 128 256 512 768 1536 768 3072 4096 1024 16 128
L2 caches per core 0, 1 (board) 1 0.5 1 1
Max. total L2 cache (MiB) 2 (board) 0.25 0.5 0.25 0.5 1 0.5 1 2 0.5 2 1 2 3 6 16 32 8 0.125 0.25
L2 cache associativity (ways) 4 2 16 8 4 16
Max. total L3 cache (MiB) N/A 2 (board) N/A 2 6 12 16 64 256 64 N/A
L3 cache associativity (ways) 32 48 64 16
L3 cache scheme victim
Max. stock DRAM support SDR DDR DDR-400 DDR2-800 DDR2-1066 DDR2-1066, DDR3-1333 DDR3-1866 DDR4-2666 DDR4-2933 DDR4-3200 EDO SDR-111 SDR-133, DDR-233 DDR-400
Max. DRAM channels per CPU 1 2 4 8 4 8 2
Max. stock DRAM bandwidth per CPU (GB/s) 6.4 12.8 17.056 21.328 42.656 51.2 59.712 170.624 93.856 204.8 51.2
  1. ^ a b c d Only marketed by Cyrix.
  2. ^ a b Only marketed by Cyrix and National Semiconductor.
  3. ^ Only marketed by National Semiconductor.
  4. ^ Marketed by National Semiconductor as GX2 and by AMD as GX.
  5. ^ A PC would be one node.
  6. ^ Including CMOV and NOPL.
  7. ^ With 64-bit processors.
  8. ^ The only Sempron CPUs that support AMD-V are Huron, Regor and Sargas.
  9. ^ Requires board support.
  10. ^ Requires firmware support.
  11. ^ No SSE4. No SSSE3.
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References


See also