Template:AMD Epyc 3000 series

Common features of EPYC Embedded 3000 series CPUs:

Socket: SP4 (31xx and 32xx models use SP4r2 package).
All the CPUs support ECC DDR4-2666 in dual-channel mode (3201 supports only DDR4-2133), while 33xx and 34xx models support quad-channel mode.
L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
L2 cache: 512 KB per core.
All the CPUs support 32 PCIe 3.0 lanes per CCD (max 64 lanes).
Fabrication process: GlobalFoundries 14 nm.

Model	Cores (threads)	Clock rate (GHz)			L3 cache (total)	TDP	Chiplets	Core config^[i]	Release date
		Base	Boost
		Base	All-core	Max
3101^[1]	4 (4)	2.1	2.9	2.9	8 MB	35 W	1 x CCD	1 × 4	Feb 2018
3151^[1]	4 (8)	2.7	2.9	2.9	16 MB	45 W		2 × 2
3201^[1]	8 (8)	1.5	3.1	3.1		30 W		2 × 4
3251^[1]	8 (16)	2.5				55 W
3255^[2]	8 (16)	2.5				25–55 W			Dec 2018
3301^[1]	12 (12)	2.0	2.15	3.0	32 MB	65 W	2 x CCD	4 × 3	Feb 2018
3351^[1]	12 (24)	1.9	2.75			60–80 W		4 × 3
3401^[1]	16 (16)	1.85	2.25			85 W		4 × 4
3451^[1]	16 (32)	2.15	2.45			80–100 W		4 × 4