The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contained 3.1 million transistors. It was fabricated by Texas Instruments (TI) at Miho, Japan in a 0.8 micrometre triple-metal[1] BiCMOS process.[2]

SuperSPARC
KL TI SuperSPARC.jpg
The SuperSPARC microprocessor
General Info
Launched1992
Discontinued1995
Designed bySun Microsystems
Performance
Max. CPU clock rate33 MHz to 90 MHz
Architecture and classification
Instruction setSPARC V8
Physical specifications
Cores
  • 1
History

There were two derivatives of the SuperSPARC: the SuperSPARC+ and SuperSPARC-II. The SuperSPARC+ was developed to remedy some of the design flaws that limited the SuperSPARC's clock frequency and thus performance. The SuperSPARC-II, introduced in 1994, was a major revision with improvements that enabled the microprocessor to reach 85 MHz in desktop systems and 90 MHz in the more heavily cooled SPARCserver-1000E.

The SuperSPARC-II was replaced in 1995 by the 64-bit UltraSPARC, an implementation of the 64-bit SPARC V9 ISA.


ModelsEdit

SuperSPARC (Viking)Edit

    • SM20: 1 CPU, no L2-Cache, 33 MHz, Bus: 33 MHz
    • SM21: 1 CPU, 1 MB L2-Cache, 33 MHz, Bus: 33 MHz (only works in early SPARCserver-2000 systems)
    • SM30: 1 CPU, no L2-Cache, 36 MHz, Bus: 36 MHz
    • SM40: 1 CPU, no L2-Cache, 40 MHz, Bus: 40 MHz
    • SM41: 1 CPU, 1 MB L2-Cache, 40.3 MHz, Bus: 40 MHz
    • SM50: 1 CPU, no L2-Cache, 50 MHz, Bus: 50 MHz
    • SM51: 1 CPU, 1 MB L2-Cache, 50 MHz, Bus: 40 MHz
    • SM51-2: 1 CPU, 2 MB L2-Cache, 50 MHz, Bus: 40 MHz
    • SM52: 2 CPU, 1 MB L2-Cache, 45 MHz, Bus: 40 MHz
    • SM52X: 2 CPU, 1 MB L2-Cache, 50 MHz, Bus: 40 MHz
    • SM61: 1 CPU, 1 MB L2-Cache, 60 MHz, Bus: 50/55 MHz
    • SM61-2: 1 CPU, 2 MB L2-Cache, 60 MHz, Bus: 50/55 MHz

SuperSPARC II (Voyager)Edit

    • SM71: 1 CPU, 1 MB L2-Cache, 75 MHz, Bus: 50 MHz
    • SM81: 1 CPU, 1 MB L2-Cache, 85 MHz, Bus: 50 MHz
    • SM81-2: 1 CPU, 2 MB L2-Cache, 85 MHz, Bus: 50/55 MHz
    • SM91-2: 1 CPU, 2 MB L2-Cache, 90 MHz, Bus: 50 MHz


ReferencesEdit

  • "TI SuperSPARC for Sun Station 3 in production". (11 May 1992). Electronic News.
  • DeTar, Jim (10 October 1994). "Sun sets SuperSPARC-II as UltraSPARC V9 bridge". Electronic News.