Maskless lithography

Maskless lithography (MPL) is a photomask-less photolithography-like technology used to project or focal-spot write the image pattern onto a chemical resist-coated substrate (e.g. wafer) by means of UV radiation or electron beam.[1]

In microlithography typically UV radiation casts an image of a time constant mask onto a photosensitive emulsion (or photoresist).[2] Traditionally mask aligners, steppers, scanners, and other kinds of non-optical techniques is used for high speed microfabrication of microstructures but in case of MPL some of these become redundant.

Maskless lithography has two approaches to project a pattern: rasterized and vectorized. In the first one it utilizes generation of a time-variant intermittent image on an electronically modifiable (virtual) mask that is projected with known means (also known as Laser Direct Imaging and other synonyms). In the vectored approach direct writing is achieved by radiation that is focused to a narrow beam that is scanned in vector form across the resist. The beam is then used to directly write the image into the photoresist, one or more pixels at a time. Also combinations of the two approaches are known and it is not limited to optical radiation, but also extends into the UV, includes electron-beams and also mechanical or thermal ablation via MEMS devices.

AdvantagesEdit

The MPL advantage is a high speed parallel manipulation of the pattern enabled by a large and cheap available computing capacity, which is not an issue with the standard approach that decouples to a slow, but precise structuring process for writing a mask from a fast and highly parallel copy process to achieve high replication throughputs as demanded by industry.

A key advantage of maskless lithography is the ability to change lithography patterns from one run to the next, without incurring the cost of generating a new photomask. This may prove useful for double patterning or compensation of non-linear material behaviour (e.g. when utilizing cheaper, non-cristalline substrate or to compensate for random placement errors of preceding structures).

DisadvantagesEdit

The main disadvantages are complexity and costs for the replication process, the limitation of rasterization in respect to oversampling causes aliasing artefact, especially with smaller structures (which may affect yield), while direct vector writing is limited in throughput. Also the digital throughput of such systems forms a bottleneck for high resolutions, i.e. structuring a 300mm diameter wafer with its area of ~707cm² requires about 10 TiB of data in a rasterized format without oversampling and thus suffers from step-artefacts (aliasing). Oversampling by a factor of 10 to reduce these artefacts adds another two orders of magnitude 1 PiB per single wafer that has to be transferred in ~1 min to the substrate to achieve high volume manufacturing speeds. Industrial maskless lithography is therefore currently only widely found for structuring lower resolution substrates, like in PCB-panel production, where resolutions ~50µm are most common (at ~2000 times lower throughput demand on the components).

FormsEdit

Currently, the main forms of maskless lithography are electron beam and optical. In addition, focused ion beam systems have established an important niche role in failure analysis and defect repair. Also, systems based on arrays of mechanical and thermally ablative probe tips have been demonstrated.

Electron beam (e-beam)Edit

The most commonly used form of maskless lithography today is electron beam lithography. Its widespread use is due to the wide range of electron beam systems available accessing an equally wide range of electron beam energies (~10 eV to ~100 keV). This is already being used in wafer-level production at eASIC, which uses conventional direct-write electron beam lithography to customize a single via layer for low-cost production of ASICs.

Most maskless lithography systems currently being developed are based on the use of multiple electron beams.[3] The goal is to use the parallel scanning of the beams to speed up the patterning of large areas. However, a fundamental consideration here is to what degree electrons from neighboring beams can disturb one another (from Coulomb repulsion). Since the electrons in parallel beams are traveling equally fast, they will persistently repel one another, while the electron lenses act over only a portion of the electrons' trajectories.

OpticalEdit

Direct laser writing is a very popular form of optical maskless lithography, which offers flexibility, ease of use, and cost effectiveness in R&D processing. This equipment offers rapid patterning at sub-micrometre resolutions, and offers a compromise between performance and cost when working with feature sizes of approximately 200 nm or greater. Direct laser writing for microelectronics packaging, 3D electronics and heterogeneous integration were developed in 1995 at the Microelectronics and Computer Technology Corporation (or MCC) in Austin, Texas.[4] The MCC system was fully integrated with precision control for 3D surfaces and artificial intelligence software with real-time machine learning and included laser wavelengths for standard i-line resist and DUV 248nm. The MCC system also included circuit editing capabilities for isolating circuits on a programmable wafer design. In 1999, the MCC system was advanced for use in MEMS manufacturing.[5]

Interference lithography or holographic exposures are not maskless processes and therefore do not count as "maskless", although they have no 1:1 imaging system in between.

Plasmonic direct writing lithography uses localized surface plasmon excitations via scanning probes to directly expose the photoresist.[6]

For improved image resolution, ultraviolet light, which has a shorter wavelength than visible light, is used to achieve resolution down to around 100 nm. The main optical maskless lithography systems in use today are the ones developed for generating photomasks for the semiconductor and LCD industries.

In 2013, a group at Swinburne University of Technology published their achievement of 9 nm feature size and 52 nm pitch, using a combination of two optical beams of different wavelengths.[7]

DLP technology can also be used for maskless lithography.[8]

Focused ion beamEdit

Focused ion beam systems are commonly used today for sputtering away defects or uncovering buried features. The use of ion sputtering must take into account the redeposition of sputtered material.

Probe-tip contactEdit

IBM Research has developed an alternative maskless lithography technique based on atomic force microscopy.[9] In addition, Dip Pen Nanolithography is a promising new approach for patterning submicrometer features.

ResearchEdit

2000sEdit

Technologies that enable maskless lithography is already used for the production of photomasks and in limited wafer-level production. There are some obstacles ahead of its use in high-volume manufacturing. First, there is a wide diversity of maskless techniques. Even within the electron-beam category, there are several vendors (Multibeam, Mapper Lithography, Canon, Advantest, Nuflare, JEOL) with entirely different architectures and beam energies. Second, throughput targets exceeding 10 wafers per hour still need to be met. Third, the capacity and ability to handle the large data volume (Tb-scale) needs to be developed and demonstrated.[citation needed]

In recent years DARPA and NIST have reduced support for maskless lithography in the U.S.[10]

There was a European program that would push the insertion of maskless lithography for IC manufacturing at the 32-nm half-pitch node in 2009.[11] Project name was MAGIC, or "MAskless lithoGraphy for IC manufacturing", in frame of EC 7th Framework Programme (FP7).[12]

Due to the increased mask costs for multiple patterning, maskless lithography is once again prompts relevant research in this field.

DarpaEdit

Since at least 2001 DARPA has invested in a variety of maskless patterning technologies including parallel e-beam arrays, parallel scanning probe arrays, and an innovative e-beam lithography tool to enable low-volume manufacturing process. The technology is codenamed as Gratings of Regular Arrays and Trim Exposures (GRATE) (previously known as Cost Effective Low Volume Nanofabrication).[13][14][15]

EconomicsEdit

FoundriesEdit

In 2018 Dutch and Russia jointly funded (Rusnano) company Mapper Lithography producing multi e-beam maskless lithography MEMS components went bankrupt and was acquired by ASML Holding, a major competitor at the time.[16][17] The foundry producing devices is located near Moscow, Russia. As of early 2019 it was run by Mapper LLC.[18] The Mapper Lithography originally was created at Delft University of Technology in 2000.[19]

ReferencesEdit

  1. ^ Walsh, M.E.; Zhang, F.; Menon, R.; Smith, H.I. (2014). "Maskless photolithography". Nanolithography. pp. 179–193. doi:10.1533/9780857098757.179. ISBN 9780857095008.
  2. ^ R. Menon et al., Materials Today, Feb. 2005, pp. 26-33 (2005).
  3. ^ T. H. P. Chang et al., Microelectronic Engineering 57-58, pp. 117-135 (2001).
  4. ^ Yee, I.; Miracky, R.; Reed, J.; Lunceford, B.; Minchuan Wang; Cobb, D.; Caldwell, G. (1997). "Flexible manufacturing of multichip modules for flip chip ICs". Proceedings 1997 IEEE Multi-Chip Module Conference. pp. 130–132. doi:10.1109/MCMC.1997.569357. ISBN 0-8186-7789-9. S2CID 111088663.
  5. ^ Hilbert, C.; Nelson, R.; Reed, J.; Lunceford, B.; Somadder, A.; Hu, K.; Ghoshal, U. (1999). "Thermoelectric MEMS coolers". Eighteenth International Conference on Thermoelectrics. Proceedings, ICT'99 (Cat. No.99TH8407). pp. 117–122. doi:10.1109/ICT.1999.843347. ISBN 0-7803-5451-6. S2CID 46697625.
  6. ^ Xie, Zhihua; Yu, Weixing; Wang, Taisheng; et al. (31 May 2011). "Plasmonic nanolithography: a review". Plasmonics. 6 (3): 565–580. doi:10.1007/s11468-011-9237-0. S2CID 119720143.
  7. ^ Gan, Zongsong; Cao, Yaoyu; Evans, Richard A.; Gu, Min (October 2013). "Three-dimensional deep sub-diffraction optical beam lithography with 9 nm feature size". Nature Communications. 4 (1): 2061. doi:10.1038/ncomms3061. PMID 23784312.
  8. ^ "Maskless Lithography tool". NanoSystem Solutions, Inc. October 17, 2017.
  9. ^ P. Vettiger et al., IBM J. Res. Dev. 44, pp. 323-340 (2000).
  10. ^ "Darpa, NIST to end funding for U.S. maskless lithography". EETimes. January 19, 2005.
  11. ^ [1] EU forms new maskless litho group
  12. ^ "CORDIS | European Commission". Archived from the original on 2008-03-28. Retrieved 2012-07-17.
  13. ^ "Department of Defense Fiscal Year (FY) 2010 Budget Estimates" (PDF). May 2009.
  14. ^ "StackPath". www.militaryaerospace.com. Retrieved 2021-06-19.
  15. ^ Fritze, M.; Tyrrell, B.; Astolfi, D.; Yost, D.; Davis, P.; Wheeler, B.; Mallen, R.; Jarmolowicz, J.; Cann, S.; Chan, D.; Rhyins, P.; Carney, C.; Ferri, J.; Blachowicz, B. A. (2001). "Gratings of regular arrays and trim exposures for ultralarge scale integrated circuit phase-shift lithography". Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 19 (6): 2366. Bibcode:2001JVSTB..19.2366F. doi:10.1116/1.1408950.
  16. ^ "ASML takes over Mapper Lithography after the bankruptcy". habr.com. Retrieved 2021-06-05.
  17. ^ Anonym. "Chip machine maker ASML buys bankrupt competitor Mapper | tellerreport.com". www.tellerreport.com. Retrieved 2021-06-05.
  18. ^ "ASML takes over Mapper Lithography after the bankruptcy". habr.com. Retrieved 2021-06-05.
  19. ^ Anonym. "Chip machine maker ASML buys bankrupt competitor Mapper | tellerreport.com". www.tellerreport.com. Retrieved 2021-06-05.

External linksEdit

  • Wieland, M. J.; De Boer, G.; Ten Berge, G. F.; Jager, R.; Van De Peut, T.; Peijster, J. J. M.; Slot, E.; Steenbrink, S. W. H. K.; Teepen, T. F.; Van Veen, A. H. V.; Kampherbeek, B. J. (2009). "MAPPER: High-throughput maskless lithography". In Schellenberg, Frank M; La Fontaine, Bruno M (eds.). Alternative Lithographic Technologies. 7271. pp. 72710O. doi:10.1117/12.814025. S2CID 173181588.
  • 35th European Mask and Lithography Conference (EMLC 2019)