In computer science, instruction selection is the stage of a compiler backend that transforms its middle-level intermediate representation (IR) into a low-level IR where each operation directly corresponds to an instruction available on the target machine. In a typical compiler, instruction selection precedes both instruction scheduling and register allocation; hence its output IR has an infinite set of pseudo-registers (often known as temporaries) and may still be – and typically is – subject to peephole optimization. Otherwise, it closely resembles the target machine code, bytecode, or assembly language.
For example, for the following sequence of middle-level IR code
t1 = a t2 = b t3 = t1 + t2 a = t3 b = t1
a good instruction sequence for the x86 architecture is
MOV EAX, a XCHG EAX, b ADD a, EAX
For a comprehensive survey on instruction selection, see.
The simplest approach to instruction selection is known as macro expansion or interpretative code generation. A macro-expanding instruction selector operates by matching templates over the middle-level IR. Upon a match the corresponding macro is executed, using the matched portion of the IR as input, which emits the appropriate target instructions. Macro expansion can be done either directly on the textual representation of the middle-level IR, or the IR can first be transformed into a graphical representation which is then traversed depth-first. In the latter, a template matches one or more adjacent nodes in the graph.
Unless the target machine is very simple, macro expansion in isolation typically generates inefficient code. To mitigate this limitation, compilers that apply this approach typically combine it with peephole optimization to replace combinations of simple instructions with more complex equivalents that increase performance and reduce code size. This is known as the Davidson-Fraser approach and is currently applied in GCC.
Another approach is to first transform the middle-level IR into a graphical representation and then cover the graph using patterns. A pattern is a template that matches a portion of the graph and can be implemented with a single instruction provided by the target machine. The goal is to cover the graph such that the total cost of the selected patterns is minimized, where the cost typically represents the number of cycles it takes to execute the instruction. For tree-shaped graphs the least-cost cover can be found in linear time using dynamic programming, but for DAGs and full-fledged graphs the problem becomes NP-complete and thus is most often solved using either greedy algorithms or methods from combinatorial optimization.
Lowest common denominator strategyEdit
This section does not cite any sources. (March 2009) (Learn how and when to remove this template message)
The lowest common denominator strategy is an instruction selection technique used on platforms where processor-supplementary instructions exist to make executable programs portable across a wide range of computers. Under a lowest common denominator strategy, the default behaviour of the compiler is to build for the lowest common architecture. Use of any available processor extension is switched off by default, unless explicitly switched on by command line switches.
The use of a lowest common denominator strategy means that processor-supplementary instructions and capabilities are not used by default.
- Hjort Blindell, Gabriel (2016). Instruction Selection: Principles, Methods, & Applications. Springer. doi:10.1007/978-3-319-34019-7. ISBN 978-3-319-34017-3.
- Brown, P. (1969). "A Survey of Macro Processors". Annual Review in Automatic Programming. 6 (2): 37–88. doi:10.1016/0066-4138(69)90001-9. ISSN 0066-4138.
- Cattell, R. G. G. (1979). "A Survey and Critique of Some Models of Code Generation" (PDF). School of Computer Science, Carnegie Mellon University (Technical report).
- Ganapathi, M.; Fischer, C. N.; Hennessy, J. L. (1982). "Retargetable Compiler Code Generation". Computing Surveys. 14 (4): 573–592. doi:10.1145/356893.356897. ISSN 0360-0300.
- Lunell, H. (1983). Code Generator Writing Systems (Doctoral thesis). Linköping, Sweden: Linköping University.
- Ammann, U.; Nori, K. V.; Jensen, K.; Nägeli, H. (1974). "The PASCAL (P) Compiler Implementation Notes". Instituts für Informatik (Technical report).
- Orgass, R. J.; Waite, W. M. (1969). "A Base for a Mobile Programming System". Communications of the ACM. 12 (9): 507–510. doi:10.1145/363219.363226.
- Wilcox, T. R. (1971). Generating Machine Code for High-Level Programming Languages (Doctoral thesis). Ithaca, New York, USA: Cornell University.
- Davidson, J. W.; Fraser, C. W. (1984). "Code Selection Through Object Code Optimization". ACM Transactions on Programming Languages and Systems. 6 (4): 505–526. CiteSeerX 10.1.1.76.3796. doi:10.1145/1780.1783. ISSN 0164-0925.
- Aho, A. V.; Ganapathi, M.; Tjiang, S. W. K. (1989). "Code Generation Using Tree Matching and Dynamic Programming". ACM Transactions on Programming Languages and Systems. 11 (4): 491–516. CiteSeerX 10.1.1.456.9102. doi:10.1145/69558.75700.
- Wilson, T.; Grewal, G.; Halley, B.; Banerji, D. (1994). An Integrated Approach to Retargetable Code Generation. Proceedings of the 7th International Symposium on High-Level Synthesis (ISSS'94). pp. 70–75. CiteSeerX 10.1.1.521.8288. doi:10.1109/ISHLS.1994.302339. ISBN 978-0-8186-5785-6.
- Bashford, S.; R., Leupers (1999). Constraint Driven Code Selection for Fixed-Point DSPs. Proceedings of the 36th Annual ACM/IEEE Design Automation Conference (DAC'99). pp. 817–822. CiteSeerX 10.1.1.331.390. doi:10.1145/309847.310076. ISBN 978-1581331097.
- Floch, A.; Wolinski, C.; Kuchcinski, K. (2010). "Combined Scheduling and Instruction Selection for Processors with Reconfigurable Cell Fabric". Proceedings of the 21st International Conference on Application-Specific Architectures and Processors (ASAP'10): 167–174.