Carbon nanotubes in interconnects

In nanotechnology, carbon nanotube interconnects refer to the proposed use of carbon nanotubes in the interconnects between the elements of an integrated circuit. Carbon nanotubes (CNTs) can be thought of as single atomic layer graphite sheets rolled up to form seamless cylinders. Depending on the direction on which they are rolled, CNTs can be semiconducting or metallic. Metallic carbon nanotubes have been identified[1] as a possible interconnect material for the future technology generations and to replace copper interconnects. Electron transport can go over long nanotube lengths, 1 μm, enabling CNTs to carry very high currents (i.e. up to a current density of 109 Acm−2) with essentially no heating due to nearly one dimensional electronic structure.[2] Despite the current saturation in CNTs at high fields,[2] the mitigation of such effects is possible due to encapsulated nanowires.[3]

Carbon nanotubes for interconnects application in Integrated chips have been studied since 2001,[4] however the extremely attractive performances of individual tubes are difficult to reach when they are assembled in large bundles necessary to make real via or lines in integrated chips. Two proposed approaches to overcome the to date limitations are either to make very tiny local connections that will be needed in future advanced chips or to make carbon metal composite structure that will be compatible with existing microelectronic processes.

Hybrid interconnects that employ CNT vias in tandem with copper interconnects may offer advantages in reliability and thermal-management.[5] In 2016, the European Union has funded a four million euro project over three years to evaluate manufacturability and performance of composite interconnects employing both CNT and copper interconnects. The project named CONNECT (CarbON Nanotube compositE InterconneCTs)[6] involves the joint efforts of seven European research and industry partners on fabrication techniques and processes to enable reliable carbon nanotubes for on-chip interconnects in ULSI microchip production.

Local interconnectsEdit

While smaller dimensions mean better performance for transistors thanks to the decrease of intrinsic transistor gate delay, the situation is quite the opposite for interconnects. Smaller cross-section areas of interconnect would only lead to performance degradation such as increased interconnect resistance and power consumption. Since the 1990s the circuit performance is no longer limited by the transistors, thus interconnects have become a key issue and are as important as the transistors in determining chip performance. As technology scaling continues, the problem of interconnect performance degradation will only become more significant. Local interconnects that are on the lower levels of the interconnect stack connecting nearby logic gates are aggressively scaled down at each generation to follow the miniaturization of transistors and thus are mostly susceptible to performance degradation. On the local level where interconnects are most densely packed, and have pitch sizes close to the minimum feature size, we will need new interconnect materials that suffer much less from sizing effects than copper.

Thanks to the measured properties of individual carbon nanotubes (CNTs), such material has been proposed as future material for interconnects.[1] Particularly their current carrying capabilities are extremely high [4] typically around 109 Acm−2 and they exhibit a ballistic length up to micrometers.[2] However, due to the strong electron-phonon interaction in single-walled CNTs, it has been discovered that electronic current undergoes saturation at the voltage bias beyond 0.2 V.[2][3]

Nevertheless, CNTs with few nm in diameter are extremely robust compared with metallic nanowires of similar diameter and demonstrate conducting properties superior as compared with copper. To make a connection, CNTs have to be paralleled in order to lower the resistance.

The resistance R of one single-walled carbon nanotubes can be expressed by

 

Where   is an extrinsic contact resistance,   is the quantum resistance (6.5 kΩ) which comes from the connection of one dimensional material to a three dimensional metal,   is the CNT length and   is the mean free path of the electron. If N tubes are paralleled, this resistance is divided by N thus one of the technological challenge is to maximize N in a given area. If L is small as compared with Lmfp, which normally is the case for very small vias, the technological parameters to optimize are primarily the contact resistance and the tube density.

Initial works have been focused on CNT vias connecting two metallic lines. Low temperature (400 °C) chemical vapor deposition growth of CNT on titanium nitride catalysed by cobalt particles has been optimized by the Fujitsu group. The catalyst particles obtained by laser ablation of a cobalt target sorted by size ultimately allow to grow a CNT density around 1012 CNT cm−2 using a multistep process using plasma and catalyst particles around 4 nm. In spite of these efforts, the electrical resistance of such via is 34 Ω _for a 160 nm diameter. Performances are close to tungsten plugs thus at least one order of magnitude higher than copper. For 60 nm via, a ballistic length of 80 nm has been determined. For processing lines, CNT technology is more difficult because dense forests of CNTs naturally grow perpendicularly to the substrate, where they are known as vertically aligned carbon nanotube arrays. Only few reports on horizontal lines have been published and rely on the redirection of CNT,[7][8] or the filling in existing trenches by fluidic assembly processes.[9] The achieved performances are around 1 mΩcm, which is two decades higher than the requested values.

The reasons for such discrepancy between theoretical expectations and achieved performances are multiple. One obvious reason is the packing density after integration, which is far from the requested values, and the one used in the theoretical prediction. Indeed, even with the CNTs, which are strongly densified and spun, low conductance remains a problem. However, a recent paper [10] shows that a one-decade improvement on the conductivity may be gained just by high-pressure densification of the CNT. In spite of the development of high-density CNT material [11] the state of the art of integrated lines is still far from the 1013 cm−2 conducting walls requested by the International Technology Roadmap for Semiconductors.[12] Nevertheless, macroscopic assemblies with diameters of tens of microns consisting of double-walled CNTs [13] or single-walled carbon nanotubes [14] have experimental resistivity performances of 15 μΩcm after doping, demonstrating the potential of CNTs for interconnects.

Global interconnectsEdit

For current metallization technologies for high-performance and low-power microelectronics, copper is the material of choice due to its higher electromigration (EM) stability (resulting from the higher melting point) and conductivity to aluminium. For downscaled logic and memory applications up to 14 nm node the increased current density and reliability requirements per interconnect line still have known material and integration solutions. Thinner barrier and adhesion layers, doping of secondary metals to enhance grain boundary electromigration resistance, and integration concepts of selective cappings will be some of the adopted solutions. However, for dimensions below 7 to 10 nm nodes, the decreased volume of available conducting metal will force innovative material and integration approaches towards novel interconnect architectures. Also for power and high-performance applications the most critical challenges are high ampacity, thermal conductivity and electromigration resistance. Far away from bulk, copper conductors that would already melt at 104 A/cm2, current copper metallization lines can withstand 107 A/cm2 due to good heat dissipation into thermal contact to the surrounding material, optimized liner and capping as well as plating and CMP processes.

The reliability of state of the art interconnects is closely linked to electromigration . This adverse effect describes the material transport and consequently void formation especially in thin metal lines to the anode by a combination of the electron wind force, the temperature gradient induced force, the stress gradient induced force and the surface tension force. Depending on the design of the interconnect layout and the used metallization scheme, the dominance of each driving force can change. Even at the current scaling node of CMOS technology, these two issues are among the main reasons for the trend that the increased density scaling of transistors no longer automatically leads to "performance scaling" (i. e. increased performance per transistor).

CNTs are being studied as a potential copper replacement owing to their excellent electrical properties in terms of conductivity, ampacity and high frequency characteristics. However, the performances of CNTs integrated into functional devices are so far systematically much lower than those of nearly perfect CNTs selected for fundamental studies worldwide. As a consequence, combinations of CNTs with copper were envisioned soon after the pioneering study about CNT interconnects.[15] Initial experimental realizations focused on a "bulk" approach where a mixture of CNTs and copper is deposited from a solution on the target substrate.[16][17][18] This approach demonstrated mitigated performances for interconnect, such that focus is now almost exclusively on composite materials where the CNTs are aligned with respect to the current flow (referred to as aligned CNT-copper composite). Furthermore, contact resistance, mechanical stability, planarity and integration could be improved by a supporting conductive matrix. Chai et al.[19][20][21] first demonstrated the fabrication of vertical interconnects using aligned CNT-copper composite materials in 2007 by first growing vertically aligned CNTs before filling the voids between CNTs with copper through an electroplating method. It was shown that this material could reach low, copper-like, resistivity but was more resistant to electromigration than copper. More recently, a renewed interest for this material was generated by the work of Hata group [22] claiming a 100 fold increase in current carrying capacity of aligned CNT-copper material compared to pure copper. Several groups are now working worldwide on the integration of aligned CNT-copper composite materials in interconnect structures,[23][24][25][26] Present and near-future efforts are focusing on demonstrating and evaluating the performances of aligned CNT-copper composite materials for both vertical and horizontal interconnects, and to develop a CMOS-compatible process flow for multilevel global interconnects.[6]

Physical and electrical characterizationEdit

Electromigration is typically characterized through the time of failure of a current carrying device.[8] The scaling of the effect with current and temperature is used for accelerated testing and predictive analysis. Despite the great technological relevance of such measurements, there exists no widely used protocol to characterize electromigration. However, certain approaches are somewhat established, such as the variation of current and temperature. One of the unresolved challenges of electromigration are self-amplification effects of electromigration through self-heating at defects in interconnect leads.[27] The local temperature rise due to current crowding across such defects is typically unknown. Since the underlying processes are typically thermally activated, the lack of precise knowledge of the local temperature makes the field of electromigration studies challenging, resulting in a lack of reproducibility and inter-comparability of different experimental approaches. A combination with in-situ temperature measurement is therefore desirable. There are numerous methods for thermometry and the measurement of thermal conductance of devices and structures on a length scale of microns to macroscopic. However, the quantitative thermal characterization of nanostructures is described as an unsolved challenge in the current scientific literature.[28][29] Several methods have been proposed using Raman spectroscopy, electron energy loss spectroscopy, infrared microscopy, self-heating methods and scanning thermal microscopy. However, on the length scale relevant to single CNTs and their defects, i. e. the 1 nm-scale, no established solution exists applicable to CNT-based materials (our interconnects) and dielectrics (our insulators and matrix materials). Scanning thermal microscopy and thermometry [30] is the most promising technique for its versatility, but restrictions in tip fabrication, operation modes and signal sensitivity have limited the resolutions to 10 nm in the most cases. To increase the resolution of such technique is an open challenge which is attracting lot of attention from the industry and scientific community.[6]

The methodology of electrical transport measurements in single CNTs, bundles and composites thereof is well established. To study finite-size effects in transport such as the transition from diffusive to ballistic transport requires the precise placement and addressing of nanoscale electrodes, typically fabricated using electron beam lithography.

Structural characterization of CNTs using transmission electron microscopy has been shown to be a useful method for structures identification and measures. Results have been reported with resolutions down to about 1 nm and very good material contact.[31] Due to the experimental difficulties of contacting nano-objects inside an electron microscope, there have only been few attempts to combine transmission electron microscopy structural characterization with in-situ electrical transport measurements.[32][33][6]

Modelling and simulationEdit

MacroscopicEdit

From a macroscopic point of view, a generalized compact RLC model for CNT interconnects can be depicted as in,[34] where the model of an individual multi-wall carbon nanotube is shown with parasitics representing both dc conductance and high-frequency impedance i.e. inductance and capacitance effects. Multiple shells of a multi-wall carbon nanotube are presented by the individual parasitics of each shell. Such model can also be applicable to single-walled carbon nanotubes where only a single shell is represented.

The shell resistance of an individual nanotube can be obtained by computing the resistance of each shell as

 

where   is the ballistic resistance,   is contact resistance,   is the distributed ohmic resistance and   is the resistance due to the applied bias voltage. Capacitance of nanotubes consists of quantum, Cq and electrostatic capacitance Ce. For multi-wall carbon nanotubes, there is the shell-to-shell coupling capacitance, Cc. Additionally there is a coupling capacitance, Ccm between any two CNT bundles. As for inductance, CNTs have both kinetic, Lk and magnetic inductance, Lm. There are also mutual inductances between shells, Mm and bundles, Mmm.

Detailed simulation for signal interconnects have been performed by Naeemi et al.,[35][36][37] and it has been shown that CNTs have lower parasitics than copper metal lines, however, the contact resistance between CNT-to-CNT and CNT-to-metal is large and can be detrimental for timing issues. Simulation on power delivery interconnects have been performed by Todri-Sanial et al.[38] and shown that CNTs overall lead to reduced voltage drop than copper interconnects.

The significant dependence of the current density between the CNTs on the geometry between them has been proved by Tsagarakis and Xanthakis.[39]

MesoscopicEdit

The macroscopic circuit simulation addresses just the interconnect performance neglecting other important aspects like reliability and variability of CNTs, which can be properly treated only at mesoscopic level by means of fully three dimensional Technology Computer Aided Design modelling approaches.[40] Recently, industrial and scientific community are investing considerable efforts to investigate the modelling of CNT variability and reliability by means of three dimensional Technology Computer Aided Design approaches for advanced technological generations.[6]

MicroscopicEdit

Underneath the macroscopic (Circuit Level) and mesoscopic (Technology Computer Aided Design level) modelling of CNT interconnects, it is also important to consider the microscopic (Ab Initio level) modelling. Significant work has been carried out on the electronic,[41][42][43][44] and thermal,[45][46] modeling of CNTs. Band structure and molecular level simulation tools can be also found on nanoHUB. Further potential modeling improvements include the self-consistent simulation of the interaction between electronic and thermal transport in CNTs, but also in copper-CNT composite lines and CNT contacts with metals and other relevant materials.

The CNTs with encapsulated nanowires have been studied at the ab initio level with self-consistent treatment of electronic and phonon transport and demonstrated to improve current-voltage performance.[3]

A fully experimentally-calibrated electrothermal modelling tool would prove useful in studying, not only the performance of CNT and composite lines, but also their reliability and variability, and the impact of the contacts on the electronic and thermal performance.[6] In this context, a full three dimensional physics-based and multi-scale (from ab-initio material simulation up to circuit simulation) simulation package that takes into account all aspects of VLSI interconnects (performance, power dissipation and reliability) is desirable to enable accurate evaluation of future CNT-based technologies.

See alsoEdit

ReferencesEdit

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